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Youn-Long Lin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jian-Wen Chen, Chao-Yang Kao, Youn-Long Lin
    Introduction to H.264 advanced video coding. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:736-741 [Conf]
  2. Hong-Kai Chang, Youn-Long Lin
    Array allocation taking into account SDRAM characteristics. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:497-502 [Conf]
  3. Yih-Chih Chou, Youn-Long Lin
    A 3-step approach for performance-driven whole-chip routing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:187-191 [Conf]
  4. Yun-Yin Lian, Youn-Long Lin
    Layout-based Logic Decomposition for Timing Optimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:229-232 [Conf]
  5. Michael C.-J. Lin, Youn-L. Lin
    A VLSI implementation of the blowfish encryption/decryption algorithm. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:1-2 [Conf]
  6. Shen-Yu Shih, Cheng-Ru Chang, Youn-Long Lin
    A near optimal deblocking filter for H.264 advanced video coding. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:170-175 [Conf]
  7. Tzu-Chieh Tien, Youn-Long Lin
    Performance-optimal clustering with retiming for sequential circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:409-414 [Conf]
  8. Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
    Test Scheduling and Test Access Architecture Optimization for System-on-Chip. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:411-0 [Conf]
  9. Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin
    Test Scheduling of BISTed Memory Cores for SOC. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:356-0 [Conf]
  10. Wei-Kai Cheng, Youn-Long Lin
    A Transformation-Based Approach for Storage Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:158-163 [Conf]
  11. Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu
    LiB: A Cell Layout Generator. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:474-479 [Conf]
  12. Chu-Yi Huang, Yen-Shen Chen, Youn-Long Lin, Yu-Chin Hsu
    Data Path Allocation Based on Bipartite Weighted Matching. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:499-504 [Conf]
  13. Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin
    Optimum and Heuristic Data Path Scheduling Under Resource Constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:65-70 [Conf]
  14. Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin
    Scheduling for Functional Pipelining and Loop Winding. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:764-769 [Conf]
  15. Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu
    An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:481-486 [Conf]
  16. Min-Siang Lin, Hourng-Wern Perng, Chi-Yi Hwang, Youn-Long Lin
    Channel Density Reduction by Routing Over The Cells. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:120-125 [Conf]
  17. Tsung-Yi Wu, Youn-Long Lin
    Register Minimization beyond Sharing among Variables. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:164-169 [Conf]
  18. Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
    A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:262-267 [Conf]
  19. Chien-Liang Chen, Jiing-Yuan Lin, Youn-Long Lin
    Integration, Verification and Layout of a Complex Multimedia SOC. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1116-1117 [Conf]
  20. Tien-Wei Hsieh, Youn-Long Lin
    A hardware accelerator IP for EBCOT Tier-1 coding in JPEG2000 Standard. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2004, pp:87-90 [Conf]
  21. Tsung-Yi Wu, Tzu-Chie Tien, Allen C.-H. Wu, Youn-Long Lin
    A Synthesis Method for Mixed Synchronous / Asynchronous Behavior. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:277-281 [Conf]
  22. Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
    Combining technology mapping and placement for delay-optimization in FPGA designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:123-127 [Conf]
  23. Yih-Chih Chou, Youn-Long Lin
    A graph-partitioning-based approach for multi-layer constrained via minimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:426-429 [Conf]
  24. Tsing-Fa Lee, Allen C.-H. Wu, Daniel Gajski, Youn-Long Lin
    An effective methodology for functional pipelining. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:230-233 [Conf]
  25. Tzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay, Yih-Chih Chou, Youn-Long Lin
    Integrating logic retiming and register placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:136-139 [Conf]
  26. Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
    State Assignment for Power and Area Minimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:250-254 [Conf]
  27. Jian-Wen Chen, Cheng-Ru Chang, Youn-Long Lin
    A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4525-4528 [Conf]
  28. Sheng-Yu Shih, Cheng-Ru Chang, Youn-Long Lin
    An AMBA-compliant deblocking filter IP for H.264/AVC. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4529-4532 [Conf]
  29. Yih-Chih Chou, Youn-Long Lin
    A performance-driven standard-cell placer based on a modified force-directed algorithm. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:24-29 [Conf]
  30. Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
    Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:12-17 [Conf]
  31. Yu-Wen Tsay, Wen-Jong Fang, Allen C.-H. Wu, Youn-Long Lin
    Preserving HDL synthesis hierarchy for cell placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:169-174 [Conf]
  32. Wei-Kai Cheng, Youn-Long Lin
    Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:15-22 [Conf]
  33. Hung-Pin Wen, Chien-Yu Lin, Youn-Long Lin
    Concurrent-simulation-based remote IP evaluation over the internet for system-on-a-chip design. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:233-238 [Conf]
  34. Yirng-An Chen, Youn-Long Lin, Long-Wen Chang
    A Systolic Algorithm for the k-Nearest Neighbors Problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:1, pp:103-108 [Journal]
  35. Yu-Chin Hsu, Youn-Long Lin, Hang-Ching Hsieh, Ting-Hai Chao
    Combining Logic Minimization and Folding for PLA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:6, pp:706-713 [Journal]
  36. Ching-Dong Chen, Yuh-Sheng Lee, Allen C.-H. Wu, Youn-Long Lin
    TRACER-fpga: a router for RAM-based FPGA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:3, pp:371-374 [Journal]
  37. Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
    Combining technology mapping and placement for delay-minimization in FPGA designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1076-1084 [Journal]
  38. Yih-Chih Chou, Youn-Long Lin
    Effective enforcement of path-delay constraints inperformance-driven placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:15-22 [Journal]
  39. Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu
    LiB: a CMOS cell compiler. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:994-1005 [Journal]
  40. Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin
    PLS: a scheduler for pipeline synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1279-1286 [Journal]
  41. Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin, Yu-Chin Hsu
    A fast transistor-chaining algorithm for CMOS cell layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:7, pp:781-786 [Journal]
  42. Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu
    An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:3, pp:410-424 [Journal]
  43. Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin
    Performance-driven interconnection optimization for microarchitecture synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:137-149 [Journal]
  44. Tsing-Fa Lee, Allen C.-H. Wu, Youn-Long Lin, Daniel D. Gajski
    A transformation-based method for loop folding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:439-450 [Journal]
  45. Youn-Long Lin, Daniel D. Gajski
    LES: a layout expert system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:8, pp:868-876 [Journal]
  46. Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
    SILK: a simulated evolution router. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:10, pp:1108-1114 [Journal]
  47. Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
    Hybrid routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:151-157 [Journal]
  48. Min-Siang Lin, Houng-Wern Perng, Chi-Yi Hwang, Youn-Long Lin
    Channel density reduction by routing over the cells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:1067-1071 [Journal]
  49. Hsiao-Pin Su, Youn-Long Lin
    A phase assignment method for virtual-wire-based hardware emulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:776-783 [Journal]
  50. Tsung-Yi Wu, Youn-Long Lin
    Register minimization beyond sharing among variables. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1583-1587 [Journal]
  51. Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
    A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:475-483 [Journal]
  52. Yu-Wen Tsay, Youn-Long Lin
    A row-based cell placement method that utilizes circuit structural properties. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:3, pp:393-397 [Journal]
  53. Wei-Kai Cheng, Youn-Long Lin
    Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1999, v:4, n:3, pp:231-256 [Journal]
  54. Youn-Long Lin
    Recent developments in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:1, pp:2-21 [Journal]
  55. Chien-Liang Chen, Jiing-Yuan Lin, Youn-Long Lin
    Integration, Verification and Layout of a Complex Multimedia SOC [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  56. A high-performance low-power H.264/AVC video decoder accelerator for embedded systems. [Citation Graph (, )][DBLP]


  57. An effective dictionary-based display frame compressor. [Citation Graph (, )][DBLP]


  58. High Performance Fractional Motion Estimation and Mode Decision for H.264/AVC. [Citation Graph (, )][DBLP]


  59. Reference frame access optimization for ultra high resolution H.264/AVC decoding. [Citation Graph (, )][DBLP]


  60. A high performance three-engine architecture for H.264/AVC fractional motion estimation. [Citation Graph (, )][DBLP]


  61. A high-performance and memory-efficient architecture for H.264/AVC motion estimation. [Citation Graph (, )][DBLP]


  62. An H.264/AVC full-mode intra-frame encoder for 1080HD video. [Citation Graph (, )][DBLP]


  63. A motion compensation system with a high efficiency reference frame pre-fetch scheme for QFHD H.264/AVC decoding. [Citation Graph (, )][DBLP]


  64. A High-Performance VLSI Architecture for Intra Prediction and Mode Decision in H.264/AVC Video Encoding. [Citation Graph (, )][DBLP]


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