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Tung-Chien Chen:
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- Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen
Hardware architecture design of an H.264/AVC video codec. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2006, pp:750-757 [Conf]
- Wei-Min Chao, Tung-Chien Chen, Yung-Chi Chang, Chih-Wei Hsu, Liang-Gee Chen
Computationally controllable integer, half, and quarter-pel motion estimator for MPEG-4 Advanced Simple Profile. [Citation Graph (0, 0)][DBLP] ISCAS (2), 2003, pp:788-791 [Conf]
- To-Wei Chen, Yu-Wen Huang, Tung-Chien Chen, Yu-Han Chen, Chuan-Yung Tsai, Liang-Gee Chen
Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos. [Citation Graph (0, 0)][DBLP] ISCAS (3), 2005, pp:2931-2934 [Conf]
- Tung-Chien Chen, Yu-Wen Huang, Chuan-Yung Tsai, Chao-Tsung Huang, Liang-Gee Chen
Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC. [Citation Graph (0, 0)][DBLP] ISCAS (2), 2005, pp:1790-1793 [Conf]
- Yu-Wen Huang, Bing-Yu Hsieh, Tung-Chien Chen, Liang-Gee Chen
Hardware architecture design for H.264/AVC intra frame coder. [Citation Graph (0, 0)][DBLP] ISCAS (2), 2004, pp:269-272 [Conf]
- Tung-Chien Chen, Yu-Wen Huang, Liang-Gee Chen
Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture. [Citation Graph (0, 0)][DBLP] ISCAS (2), 2004, pp:273-276 [Conf]
- Tung-Chien Chen, Shao-Yi Chien, Yu-Wen Huang, Chen-Han Tsai, Ching-Yeh Chen, To-Wei Chen, Liang-Gee Chen
Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder. [Citation Graph (0, 0)][DBLP] IEEE Trans. Circuits Syst. Video Techn., 2006, v:16, n:6, pp:673-688 [Journal]
- Yu-Wen Huang, Bing-Yu Hsieh, Tung-Chien Chen, Liang-Gee Chen
Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder. [Citation Graph (0, 0)][DBLP] IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:3, pp:378-401 [Journal]
- Pei-Kuei Tsung, Li-Fu Ding, Wei-Yin Chen, Shao-Yi Chien, Tung-Chien Chen, Liang-Gee Chen
System Bandwidth Analysis of Multiview Video Coding with Precedence Constraint. [Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:1001-1004 [Conf]
- Tung-Chien Chen, Yu-Han Chen, Chuan-Yung Tsai, Liang-Gee Chen
Low power and power aware fractional motion estimation of H.264/AVC for mobile applications. [Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf]
- Tung-Chien Chen, Chuan-Yung Tsai, Yu-Wen Huang, Liang-Gee Chen
Single Reference Frame Multiple Current Macroblocks Scheme for Multiple Reference Frame Motion Estimation in H.264/AVC. [Citation Graph (0, 0)][DBLP] IEEE Trans. Circuits Syst. Video Techn., 2007, v:17, n:2, pp:242-247 [Journal]
Power-Scalable Algorithm and Reconfigurable Macro-Block Pipelining Architecture of H.264 Encoder for Mobile Application. [Citation Graph (, )][DBLP]
Low Power Entropy Coding Hardware Design for H.264/AVC Baseline Profile Encoder. [Citation Graph (, )][DBLP]
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