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Sarvesh Bhardwaj: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula
    Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:953-958 [Conf]
  2. Vineet Agarwal, Navneeth Kankani, Ravishankar Rao, Sarvesh Bhardwaj, Janet Wang
    An efficient combinationality check technique for the synthesis of cyclic combinational circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:212-215 [Conf]
  3. Sarvesh Bhardwaj, Sarma B. K. Vrudhula
    Leakage minimization of nano-scale circuits in the presence of systematic and random variations. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:541-546 [Conf]
  4. Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Praveen Ghanta, Yu Cao
    Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:791-796 [Conf]
  5. Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhardwaj, Rajendran Panda
    Stochastic variational analysis of large power grids considering intra-die correlations. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:211-216 [Conf]
  6. Sarvesh Bhardwaj, Sarma B. K. Vrudhula
    Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:713-718 [Conf]
  7. Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw
    Estimation of signal arrival times in the presence of delay noise. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:418-422 [Conf]
  8. Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw
    AU: Timing Analysis Under Uncertainty. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:615-620 [Conf]
  9. Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula
    A framework for statistical timing analysis using non-linear delay and slew models. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:225-230 [Conf]
  10. Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula
    LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:717-722 [Conf]
  11. Kaviraj Chopra, Sarma B. K. Vrudhula, Sarvesh Bhardwaj
    Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:240-0 [Conf]
  12. Sarma B. K. Vrudhula, Sarvesh Bhardwaj
    Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:9- [Conf]
  13. Sarvesh Bhardwaj, Sarma B. K. Vrudhula
    A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:589-594 [Conf]
  14. Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw
    Probability distribution of signal arrival times using Bayesian networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1784-1794 [Journal]
  15. Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Rakesh Vattikonda, Sarma B. K. Vrudhula, Frank Liu, Yu Cao
    The Impact of NBTI on the Performance of Combinational and Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:364-369 [Conf]
  16. Amit Goel, Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula
    Computation of Joint Timing Yield of Sequential Networks Considering Process Variations. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:125-137 [Conf]
  17. Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula
    Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:2, pp:240-250 [Journal]

  18. Temperature and Process Variations Aware Power Gating of Functional Units. [Citation Graph (, )][DBLP]


  19. Power Reduction of Functional Units Considering Temperature and Process Variations. [Citation Graph (, )][DBLP]


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