Search the dblp DataBase
Sarma B. K. Vrudhula :
[Publications ]
[Author Rank by year ]
[Co-authors ]
[Prefers ]
[Cites ]
[Cited by ]
Publications of Author
Sarvesh Bhardwaj , Yu Cao , Sarma B. K. Vrudhula Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2006, pp:953-958 [Conf ] Ravishankar Rao , Sarma B. K. Vrudhula , Musaravakkam S. Krishnan Disk drive energy optimization for audio-video applications. [Citation Graph (0, 0)][DBLP ] CASES, 2004, pp:93-103 [Conf ] Daler N. Rakhmatov , Sarma B. K. Vrudhula Hardware-software bipartitioning for dynamically reconfigurable systems. [Citation Graph (0, 0)][DBLP ] CODES, 2002, pp:145-150 [Conf ] Aseem Agarwal , David Blaauw , Vladimir Zolotov , Sarma B. K. Vrudhula Computation and Refinement of Statistical Bounds on Circuit Delay. [Citation Graph (0, 0)][DBLP ] DAC, 2003, pp:348-353 [Conf ] Kanak Agarwal , Dennis Sylvester , David Blaauw , Frank Liu , Sani R. Nassif , Sarma B. K. Vrudhula Variational delay metrics for interconnect timing analysis. [Citation Graph (0, 0)][DBLP ] DAC, 2004, pp:381-384 [Conf ] Sarvesh Bhardwaj , Sarma B. K. Vrudhula Leakage minimization of nano-scale circuits in the presence of systematic and random variations. [Citation Graph (0, 0)][DBLP ] DAC, 2005, pp:541-546 [Conf ] Sarvesh Bhardwaj , Sarma B. K. Vrudhula , Praveen Ghanta , Yu Cao Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits. [Citation Graph (0, 0)][DBLP ] DAC, 2006, pp:791-796 [Conf ] Kaviraj Chopra , Sarma B. K. Vrudhula Implicit pseudo boolean enumeration algorithms for input vector control. [Citation Graph (0, 0)][DBLP ] DAC, 2004, pp:767-772 [Conf ] Youngjin Cho , Naehyuck Chang , Chaitali Chakrabarti , Sarma B. K. Vrudhula High-level power management of embedded systems with application-specific energy cost functions. [Citation Graph (0, 0)][DBLP ] DAC, 2006, pp:568-573 [Conf ] Praveen Ghanta , Sarma B. K. Vrudhula , Sarvesh Bhardwaj , Rajendran Panda Stochastic variational analysis of large power grids considering intra-die correlations. [Citation Graph (0, 0)][DBLP ] DAC, 2006, pp:211-216 [Conf ] Yung-Te Lai , Massoud Pedram , Sarma B. K. Vrudhula BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis. [Citation Graph (0, 0)][DBLP ] DAC, 1993, pp:642-647 [Conf ] Ravishankar Rao , Sarma B. K. Vrudhula Energy optimal speed control of devices with discrete speed sets. [Citation Graph (0, 0)][DBLP ] DAC, 2005, pp:901-904 [Conf ] Sreeja Raj , Sarma B. K. Vrudhula , Janet Meiling Wang A methodology to improve timing yield in the presence of process variations. [Citation Graph (0, 0)][DBLP ] DAC, 2004, pp:448-453 [Conf ] Daler N. Rakhmatov , Sarma B. K. Vrudhula , Chaitali Chakrabarti Battery-conscious task sequencing for portable devices including voltage/clock scaling. [Citation Graph (0, 0)][DBLP ] DAC, 2002, pp:189-194 [Conf ] Sarma B. K. Vrudhula , David Blaauw , Supamas Sirichotiyakul Estimation of the likelihood of capacitive coupling noise. [Citation Graph (0, 0)][DBLP ] DAC, 2002, pp:653-658 [Conf ] Qi Wang , Sarma B. K. Vrudhula , Shantanu Ganguly An Investigation of Power Delay Trade-Offs on PowerPC Circuits. [Citation Graph (0, 0)][DBLP ] DAC, 1997, pp:425-428 [Conf ] Jianli Zhuo , Chaitali Chakrabarti , Naehyuck Chang , Sarma B. K. Vrudhula Extending the lifetime of fuel cell based hybrid systems. [Citation Graph (0, 0)][DBLP ] DAC, 2006, pp:562-567 [Conf ] Aseem Agarwal , David Blaauw , Vladimir Zolotov , Sarma B. K. Vrudhula Statistical Timing Analysis Using Bounds. [Citation Graph (0, 0)][DBLP ] DATE, 2003, pp:10062-10067 [Conf ] Sridhar Dasika , Sarma B. K. Vrudhula , Kaviraj Chopra , R. Srinivasan A Framework for Battery-Aware Sensor Management. [Citation Graph (0, 0)][DBLP ] DATE, 2004, pp:962-967 [Conf ] Praveen Ghanta , Sarma B. K. Vrudhula , Rajendran Panda , Janet Meiling Wang Stochastic Power Grid Analysis Considering Process Variations. [Citation Graph (0, 0)][DBLP ] DATE, 2005, pp:964-969 [Conf ] Qi Wang , Sarma B. K. Vrudhula Data Driven Power Optimization of Sequential Circuits. [Citation Graph (0, 0)][DBLP ] DATE, 1998, pp:686-691 [Conf ] Krzysztof S. Berezowski , Sarma B. K. Vrudhula Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series. [Citation Graph (0, 0)][DBLP ] DSD, 2005, pp:139-143 [Conf ] Tejaswi Gowda , Sarma B. K. Vrudhula , Goran Konjevod Combinational equivalence checking for threshold logic circuits. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2007, pp:102-107 [Conf ] Sarvesh Bhardwaj , Sarma B. K. Vrudhula Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:713-718 [Conf ] Sarvesh Bhardwaj , Sarma B. K. Vrudhula , David Blaauw Estimation of signal arrival times in the presence of delay noise. [Citation Graph (0, 0)][DBLP ] ICCAD, 2002, pp:418-422 [Conf ] Sarvesh Bhardwaj , Sarma B. K. Vrudhula , David Blaauw AU: Timing Analysis Under Uncertainty. [Citation Graph (0, 0)][DBLP ] ICCAD, 2003, pp:615-620 [Conf ] Yung-Te Lai , Massoud Pedram , Sarma B. K. Vrudhula FGILP: an integer linear program solver based on function graphs. [Citation Graph (0, 0)][DBLP ] ICCAD, 1993, pp:685-689 [Conf ] Daler N. Rakhmatov , Sarma B. K. Vrudhula An Analytical High-Level Battery Model for Use in Energy Management of Portable Electronic Systems. [Citation Graph (0, 0)][DBLP ] ICCAD, 2001, pp:488-493 [Conf ] Ravishankar Rao , Sarma B. K. Vrudhula Energy optimization for a two-device data flow chain. [Citation Graph (0, 0)][DBLP ] ICCAD, 2004, pp:268-274 [Conf ] Ravishankar Rao , Sarma B. K. Vrudhula Battery optimization vs energy optimization: which to choose and when? [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:439-445 [Conf ] Janet Meiling Wang , Praveen Ghanta , Sarma B. K. Vrudhula Stochastic analysis of interconnect performance in the presence of process variations. [Citation Graph (0, 0)][DBLP ] ICCAD, 2004, pp:880-886 [Conf ] Qi Wang , Sarma B. K. Vrudhula Multi-level logic optimization for low power using local logic transformations. [Citation Graph (0, 0)][DBLP ] ICCAD, 1996, pp:270-277 [Conf ] Qi Wang , Sarma B. K. Vrudhula Static power optimization of deep submicron CMOS circuits for dual VT technology. [Citation Graph (0, 0)][DBLP ] ICCAD, 1998, pp:490-496 [Conf ] Sarvesh Bhardwaj , Praveen Ghanta , Sarma B. K. Vrudhula A framework for statistical timing analysis using non-linear delay and slew models. [Citation Graph (0, 0)][DBLP ] ICCAD, 2006, pp:225-230 [Conf ] Qi Wang , Sarma B. K. Vrudhula An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits. [Citation Graph (0, 0)][DBLP ] ICCD, 1999, pp:556-562 [Conf ] Daler N. Rakhmatov , Sarma B. K. Vrudhula Minimizing routing configuration cost in dynamically reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP ] IPDPS, 2001, pp:145- [Conf ] Daler N. Rakhmatov , Sarma B. K. Vrudhula Time-to-failure estimation for batteries in portable electronic systems. [Citation Graph (0, 0)][DBLP ] ISLPED, 2001, pp:88-91 [Conf ] Daler N. Rakhmatov , Sarma B. K. Vrudhula , Deborah A. Wallach Battery lifetime prediction for energy-aware computing. [Citation Graph (0, 0)][DBLP ] ISLPED, 2002, pp:154-159 [Conf ] Ravishankar Rao , Sarma B. K. Vrudhula , Daler N. Rakhmatov Analysis of discharge techniques for multiple battery systems. [Citation Graph (0, 0)][DBLP ] ISLPED, 2003, pp:44-47 [Conf ] Ravishankar Rao , Sarma B. K. Vrudhula , Chaitali Chakrabarti , Naehyuck Chang An optimal analytical solution for processor speed control with thermal constraints. [Citation Graph (0, 0)][DBLP ] ISLPED, 2006, pp:292-297 [Conf ] Jianli Zhuo , Chaitali Chakrabarti , Naehyuck Chang , Sarma B. K. Vrudhula Maximizing the lifetime of embedded systems powered by fuel cell-battery hybrids. [Citation Graph (0, 0)][DBLP ] ISLPED, 2006, pp:424-429 [Conf ] Sarvesh Bhardwaj , Yu Cao , Sarma B. K. Vrudhula LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs. [Citation Graph (0, 0)][DBLP ] ISQED, 2006, pp:717-722 [Conf ] Praveen Ghanta , Sarma B. K. Vrudhula Variational Interconnect Delay Metrics for Statistical Timing Analysis. [Citation Graph (0, 0)][DBLP ] ISQED, 2006, pp:19-24 [Conf ] Tao Shu , Marwan Krunz , Sarma B. K. Vrudhula Power balanced coverage-time optimization for clustered wireless sensor networks. [Citation Graph (0, 0)][DBLP ] MobiHoc, 2005, pp:111-120 [Conf ] Aseem Agarwal , David Blaauw , Vladimir Zolotov , Sarma B. K. Vrudhula Statistical timing analysis using bounds and selective enumeration. [Citation Graph (0, 0)][DBLP ] Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:16-21 [Conf ] Aseem Agarwal , David Blaauw , Vladimir Zolotov , Sarma B. K. Vrudhula Statistical timing analysis using bounds and selective enumeration. [Citation Graph (0, 0)][DBLP ] Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:29-36 [Conf ] Kaviraj Chopra , Sarma B. K. Vrudhula , Sarvesh Bhardwaj Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2004, pp:240-0 [Conf ] Raghukiran Sreeramaneni , Sarma B. K. Vrudhula Energy Profiler for Hardware/Software Co-Design. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2004, pp:335-0 [Conf ] Sarma B. K. Vrudhula , Sarvesh Bhardwaj Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2007, pp:9- [Conf ] Sarvesh Bhardwaj , Sarma B. K. Vrudhula A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2007, pp:589-594 [Conf ] Ravishankar Rao , Sarma B. K. Vrudhula , Daler N. Rakhmatov Battery Modeling for Energy-Aware System Design. [Citation Graph (0, 0)][DBLP ] IEEE Computer, 2003, v:36, n:12, pp:77-87 [Journal ] Daler N. Rakhmatov , Sarma B. K. Vrudhula , Thomas J. Brown , Ajay Nagarandal Adaptive Multiuser Online Reconfigurable Engine. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2000, v:17, n:1, pp:53-67 [Journal ] Yung-Te Lai , Massoud Pedram , Sarma B. K. Vrudhula Formal Verification Using Edge-Valued Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1996, v:45, n:2, pp:247-255 [Journal ] Amitava Majumdar , Sarma B. K. Vrudhula Fault Coverage and Test Length Estimation for Random Pattern Testing. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1995, v:44, n:2, pp:234-247 [Journal ] King C. Ho , Sarma B. K. Vrudhula Interval graph algorithms for two-dimensional multiple folding of array-based VLSI layouts. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:10, pp:1201-1222 [Journal ] Sarvesh Bhardwaj , Sarma B. K. Vrudhula , David Blaauw Probability distribution of signal arrival times using Bayesian networks. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1784-1794 [Journal ] Yung-Te Lai , Massoud Pedram , Sarma B. K. Vrudhula EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:8, pp:959-975 [Journal ] Sarma B. K. Vrudhula , David T. Blaauw , Supamas Sirichotiyakul Probabilistic analysis of interconnect coupling noise. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1188-1203 [Journal ] Sarma B. K. Vrudhula , Janet Meiling Wang , Praveen Ghanta Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2001-2011 [Journal ] Qi Wang , Sarma B. K. Vrudhula Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:3, pp:306-318 [Journal ] Daler N. Rakhmatov , Sarma B. K. Vrudhula Energy management for battery-powered embedded systems. [Citation Graph (0, 0)][DBLP ] ACM Trans. Embedded Comput. Syst., 2003, v:2, n:3, pp:277-324 [Journal ] Haibo Wang , Sarma B. K. Vrudhula Behavioral synthesis of field programmable analog array circuits. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:4, pp:563-604 [Journal ] Qi Wang , Sarma B. K. Vrudhula , Gary K. H. Yeap , Shantanu Ganguly Power reduction and power-delay trade-offs using logic transformations. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 1999, v:4, n:1, pp:97-121 [Journal ] Ravishankar Rao , Sarma B. K. Vrudhula Performance optimal processor throttling under thermal constraints. [Citation Graph (0, 0)][DBLP ] CASES, 2007, pp:257-266 [Conf ] Wenping Wang , Shengqi Yang , Sarvesh Bhardwaj , Rakesh Vattikonda , Sarma B. K. Vrudhula , Frank Liu , Yu Cao The Impact of NBTI on the Performance of Combinational and Sequential Circuits. [Citation Graph (0, 0)][DBLP ] DAC, 2007, pp:364-369 [Conf ] Amit Goel , Sarvesh Bhardwaj , Praveen Ghanta , Sarma B. K. Vrudhula Computation of Joint Timing Yield of Sequential Networks Considering Process Variations. [Citation Graph (0, 0)][DBLP ] PATMOS, 2007, pp:125-137 [Conf ] Praveen Ghanta , Sarma B. K. Vrudhula , Rajendran Panda , Janet Wang Stochastic Power Grid Analysis Considering Process Variations [Citation Graph (0, 0)][DBLP ] CoRR, 2007, v:0, n:, pp:- [Journal ] Ravishankar Rao , Sarma B. K. Vrudhula Energy optimal speed control of a producer--consumer device pair. [Citation Graph (0, 0)][DBLP ] ACM Trans. Embedded Comput. Syst., 2007, v:6, n:4, pp:- [Journal ] T.-Y. Wuu , Sarma B. K. Vrudhula A design of a fast and area efficient multi-input Muller C-element. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:215-219 [Journal ] Amitava Majumdar , Sarma B. K. Vrudhula Analysis of signal probability in logic circuits using stochastic models. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1993, v:1, n:3, pp:365-379 [Journal ] Daler N. Rakhmatov , Sarma B. K. Vrudhula , Deborah A. Wallach A model for battery lifetime analysis for organizing applications on a pocket computer. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1019-1030 [Journal ] Sarvesh Bhardwaj , Yu Cao , Sarma B. K. Vrudhula Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection. [Citation Graph (0, 0)][DBLP ] J. Low Power Electronics, 2006, v:2, n:2, pp:240-250 [Journal ] Decomposition based approach for synthesis of multi-level threshold logic circuits. [Citation Graph (, )][DBLP ] A scalable parallel H.264 decoder on the cell broadband engine architecture. [Citation Graph (, )][DBLP ] Statistical waveform and current source based standard cell models for accurate timing analysis. [Citation Graph (, )][DBLP ] Throughput optimal task allocation under thermal constraints for multi-core processors. [Citation Graph (, )][DBLP ] Current source based standard cell model for accurate signal integrity and timing analysis. [Citation Graph (, )][DBLP ] Performance optimal speed control of multi-core processors under thermal constraints. [Citation Graph (, )][DBLP ] Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors. [Citation Graph (, )][DBLP ] Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control. [Citation Graph (, )][DBLP ] Analytical results for design space exploration of multi-core processors employing thread migration. [Citation Graph (, )][DBLP ] Throughput of multi-core processors under thermal constraints. [Citation Graph (, )][DBLP ] Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices. [Citation Graph (, )][DBLP ] A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design. [Citation Graph (, )][DBLP ] A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations. [Citation Graph (, )][DBLP ] Temperature and Process Variations Aware Power Gating of Functional Units. [Citation Graph (, )][DBLP ] Power Reduction of Functional Units Considering Temperature and Process Variations. [Citation Graph (, )][DBLP ] Threshold Logic Gene Regulatory Model - Prediction of Dorsal-ventral Patterning and Hardware-based Simulation of Drosophila. [Citation Graph (, )][DBLP ] Analysis of Power Supply Noise in the Presence of Process Variations. [Citation Graph (, )][DBLP ] Search in 0.009secs, Finished in 0.013secs