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Cristinel Ababei: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Cristinel Ababei, Hushrav Mogal, Kia Bazargan
    Three-dimensional place and route for FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:773-778 [Conf]
  2. Pongstorn Maidee, Cristinel Ababei, Kia Bazargan
    Fast timing-driven partitioning-based placement for island style FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:598-603 [Conf]
  3. Cristinel Ababei, Kia Bazargan
    Statistical Timing Driven Partitioning for VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1109- [Conf]
  4. Cristinel Ababei, Hushrav Mogal, Kia Bazargan
    3D FPGAs: placement, routing, and architecture evaluation (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:263- [Conf]
  5. Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh
    HARP: hard-wired routing pattern FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:21-29 [Conf]
  6. Cristinel Ababei
    TPR: Three-D Place and Route for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1172- [Conf]
  7. Cristinel Ababei, Pongstorn Maidee, Kia Bazargan
    Exploring Potential Benefits of 3D FPGA Integration. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:874-880 [Conf]
  8. Cristinel Ababei, Kia Bazargan
    Placement Method Targeting Predictability Robustness and Performance. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:81-85 [Conf]
  9. Cristinel Ababei, Navaratnasothie Selvakkumaran, Kia Bazargan, George Karypis
    Multi-objective circuit partitioning for cutsize and path-based delay minimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:181-185 [Conf]
  10. Cristinel Ababei, Kia Bazargan
    Non-Contiguous Linear Placement for Reconfigurable Fabrics. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  11. Cristinel Ababei, Kia Bazargan
    Timing Minimization by Statistical Timing hMetis-based Partitioning. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:58-63 [Conf]
  12. Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar
    Placement and Routing in 3D Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:6, pp:520-531 [Journal]
  13. Cristinel Ababei, Hushrav Mogal, Kia Bazargan
    Three-dimensional place and route for FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1132-1140 [Journal]
  14. Pongstorn Maidee, Cristinel Ababei, Kia Bazargan
    Timing-driven partitioning-based placement for island style FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:395-406 [Journal]
  15. Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Elaheh Bozorgzadeh
    Statistical Analysis and Design of HARP FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2088-2102 [Journal]

  16. Network on chip design and optimization using specialized influence models. [Citation Graph (, )][DBLP]


  17. Parallel placement for FPGAs revisited. [Citation Graph (, )][DBLP]


  18. Achieving network on chip fault tolerance by adaptive remapping. [Citation Graph (, )][DBLP]


  19. A Framework for 2.5D NoC Exploration Using Homogeneous Networks over Heterogeneous Floorplans. [Citation Graph (, )][DBLP]


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