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M. Balakrishnan:
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Publications of Author
- Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar
Exploring the Number of Register Windows in ASIP Synthesis. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2002, pp:233-238 [Conf]
- Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan
A New Divide and Conquer Method for Achieving High Speed Division in Hardware. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2002, pp:535-540 [Conf]
- Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
An efficient technique for exploring register file size in ASIP synthesis. [Citation Graph (0, 0)][DBLP] CASES, 2002, pp:252-261 [Conf]
- Basant Kumar Dwivedi, Jan Hoogerbrugge, Paul Stravers, M. Balakrishnan
Exploring design space of parallel realizations: MPEG-2 decoder case study. [Citation Graph (0, 0)][DBLP] CODES, 2001, pp:92-97 [Conf]
- Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan
Automatic synthesis of system on chip multiprocessor architectures for process networks. [Citation Graph (0, 0)][DBLP] CODES+ISSS, 2004, pp:60-65 [Conf]
- Rajeshwari Banakar, Stefan Steinke, Bo-Sik Lee, M. Balakrishnan, Peter Marwedel
Scratchpad memory: design alternative for cache on-chip memory in embedded systems. [Citation Graph (0, 0)][DBLP] CODES, 2002, pp:73-78 [Conf]
- Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, Peter Marwedel, M. Balakrishnan
Evaluating register file size in ASIP design. [Citation Graph (0, 0)][DBLP] CODES, 2001, pp:109-114 [Conf]
- M. Balakrishnan, Peter Marwedel
Integrated Scheduling and Binding: A Synthesis Approach for Design Space Exploration. [Citation Graph (0, 0)][DBLP] DAC, 1989, pp:68-74 [Conf]
- Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. [Citation Graph (0, 0)][DBLP] DATE, 2005, pp:730-735 [Conf]
- Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
Exploring Storage Organization in ASIP Synthesis. [Citation Graph (0, 0)][DBLP] DSD, 2003, pp:120-127 [Conf]
- Harsh Dhand, Basant Kumar Dwivedi, M. Balakrishnan
New approach to architectural synthesis: incorporating QoS constraint. [Citation Graph (0, 0)][DBLP] EMSOFT, 2006, pp:301-310 [Conf]
- M. Anand, Sanjiv Kapoor, M. Balakrishnan
Hardware/Software Partitioning Between Microprocessor and Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP] FPGA, 1999, pp:249- [Conf]
- Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, Subhashis Banerjee
SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only). [Citation Graph (0, 0)][DBLP] FPGA, 2005, pp:273- [Conf]
- A. R. Naseer, M. Balakrishnan, Anshul Kumar
An Efficient Technique for Mapping RTL Structures onto FPGAs. [Citation Graph (0, 0)][DBLP] FPL, 1994, pp:99-110 [Conf]
- A. R. Naseer, M. Balakrishnan, Anshul Kumar
Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs. [Citation Graph (0, 0)][DBLP] FPL, 1995, pp:139-148 [Conf]
- M. Balakrishnan
Buffer constraints in a variable-rate packetized video system. [Citation Graph (0, 0)][DBLP] ICIP, 1995, pp:29-32 [Conf]
- M. Balakrishnan, R. Cohen
Global Optimization of Multiplexed Video Encoders. [Citation Graph (0, 0)][DBLP] ICIP (1), 1997, pp:377-0 [Conf]
- Atul Varshneya, B. B. Madan, M. Balakrishnan
Concurrent Search and Insertion in K-Dimensional Height Balanced Trees. [Citation Graph (0, 0)][DBLP] IPPS, 1994, pp:883-887 [Conf]
- Akshaye Sama, J. F. M. Theeuwen, M. Balakrishnan
Speeding up power estimation of embedded software. [Citation Graph (0, 0)][DBLP] ISLPED, 2000, pp:191-196 [Conf]
- M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha
A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. [Citation Graph (0, 0)][DBLP] ISSS, 2002, pp:2-7 [Conf]
- M. Balakrishnan, Anshul Kumar, C. P. Joshi
A New Performance Evaluation Approach for System Level Design Space Exploration. [Citation Graph (0, 0)][DBLP] ISSS, 2002, pp:180-185 [Conf]
- M. Balakrishnan, Peter Marwedel, Lars Wehmeyer, Nils Grunwald, Rajeshwari Banakar, Stefan Steinke
Reducing Energy Consumption by Dynamic Copying of Instructions onto Onchip Memory. [Citation Graph (0, 0)][DBLP] ISSS, 2002, pp:213-218 [Conf]
- M. Balakrishnan
A Specialized Graduate Program in VLSI Design: A Success Story. [Citation Graph (0, 0)][DBLP] MSE, 2001, pp:85-86 [Conf]
- M. Balakrishnan, B. S. Panwar
A Specialized Graduate Program in VLSI Design Tools and Technology. [Citation Graph (0, 0)][DBLP] MSE, 2005, pp:83-84 [Conf]
- Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrishnan, Anshul Kumar
Rapid Resource-Constrained Hardware Performance Estimation. [Citation Graph (0, 0)][DBLP] IEEE International Workshop on Rapid System Prototyping, 2006, pp:40-46 [Conf]
- Gaurav Aggarwal, Nitin Thaper, Kamal Aggarwal, M. Balakrishnan, Shashi Kumar
A Novel Reconfigurable Co-Processor Architecture. [Citation Graph (0, 0)][DBLP] VLSI Design, 1997, pp:370-375 [Conf]
- C. S. Ajay, M. Balakrishnan, D. Harikrishna, M. Karunakaran, Anshul Kumar, Shashi Kumar, V. Mudgil, A. R. Naseer
High Level Design Experiences with IDEAS. [Citation Graph (0, 0)][DBLP] VLSI Design, 1993, pp:110- [Conf]
- Gaurav Arora, Abhishek Sharma, D. Nagchoudhuri, M. Balakrishnan
ADOPT: An Approach to Activity Based Delay Optimization. [Citation Graph (0, 0)][DBLP] VLSI Design, 2005, pp:411-416 [Conf]
- Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar
Exploring the Number of Register Windows in ASIP Synthesis. [Citation Graph (0, 0)][DBLP] VLSI Design, 2002, pp:233-238 [Conf]
- Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan
Synthesis of Application Specific Multiprocessor Architectures for Process Networks. [Citation Graph (0, 0)][DBLP] VLSI Design, 2004, pp:780-783 [Conf]
- T. Vinod Kumar Gupta, Purvesh Sharma, M. Balakrishnan, Sharad Malik
Processor Evaluation in an Embedded Systems Design Environment. [Citation Graph (0, 0)][DBLP] VLSI Design, 2000, pp:98-103 [Conf]
- Rashmi Goswami, V. Srinivasan, M. Balakrishnan
MPEG-2 Video Data Simulator: A Case Study in Constrained HW-SW Codesign. [Citation Graph (0, 0)][DBLP] VLSI Design, 1999, pp:128-132 [Conf]
- Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
ASIP Design Methodologies : Survey and Issues. [Citation Graph (0, 0)][DBLP] VLSI Design, 2001, pp:76-0 [Conf]
- Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
Integrated On-Chip Storage Evaluation in ASIP Synthesis. [Citation Graph (0, 0)][DBLP] VLSI Design, 2005, pp:274-279 [Conf]
- Heman Khanna, M. Balakrishnan
Allocation of FIFO Structures in RTL Data Paths. [Citation Graph (0, 0)][DBLP] VLSI Design, 1997, pp:130-133 [Conf]
- Sitanshu Jain, M. Balakrishnan, Anshul Kumar, Shashi Kumar
Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library. [Citation Graph (0, 0)][DBLP] VLSI Design, 1998, pp:400-405 [Conf]
- Alok Kumar, Anshul Kumar, M. Balakrishnan
Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis. [Citation Graph (0, 0)][DBLP] VLSI Design, 1995, pp:75-80 [Conf]
- Anmol Mathur, Masahiro Fujita, M. Balakrishnan, Raj S. Mitra
Sequential Equivalence Checking. [Citation Graph (0, 0)][DBLP] VLSI Design, 2006, pp:18-19 [Conf]
- Sandeep K. Lodha, Shashank Gupta, M. Balakrishnan, Subhashis Banerjee
Real Time Collision Detection and Avoidance: A Case Study for Design Space Exploration in HW-SW Codesign. [Citation Graph (0, 0)][DBLP] VLSI Design, 1998, pp:97-0 [Conf]
- Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan
A New Divide and Conquer Method for Achieving High Speed Division in Hardware. [Citation Graph (0, 0)][DBLP] VLSI Design, 2002, pp:535-540 [Conf]
- A. R. Naseer, M. Balakrishnan, Anshul Kumar
FAST: FPGA Targeted RTL Structure Synthesis Technique. [Citation Graph (0, 0)][DBLP] VLSI Design, 1994, pp:21-24 [Conf]
- A. R. Naseer, M. Balakrishnan, Anshul Kumar
Optimal Clock Period for Synthesized Data Paths. [Citation Graph (0, 0)][DBLP] VLSI Design, 1997, pp:134-139 [Conf]
- Arvind Rajawat, M. Balakrishnan, Anshul Kumar
nterface Synthesis: Issues and Approaches. [Citation Graph (0, 0)][DBLP] VLSI Design, 2000, pp:92- [Conf]
- M. V. Rao, M. Balakrishnan, Anshul Kumar
DESSERT: Design Space Exploration of RT Level Components. [Citation Graph (0, 0)][DBLP] VLSI Design, 1993, pp:299-304 [Conf]
- Anupam Rastogi, M. Balakrishnan, Anshul Kumar
Integrating Communication Cost Estimation in Embedded Systems Design : A PCI Case Study. [Citation Graph (0, 0)][DBLP] VLSI Design, 2001, pp:23-28 [Conf]
- Ajoy C. Siddabathuni, M. Balakrishnan
Simulation and Modeling of a Multicast ATM Switch. [Citation Graph (0, 0)][DBLP] VLSI Design, 1999, pp:242-0 [Conf]
- Aviral Shrivastava, Mohit Kumar, Sanjiv Kapoor, Shashi Kumar, M. Balakrishnan
Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming. [Citation Graph (0, 0)][DBLP] VLSI Design, 2000, pp:110-113 [Conf]
- Amarjeet Singh 0002, Amit Chhabra, Anup Gangwar, Basant Kumar Dwivedi, M. Balakrishnan, Anshul Kumar
SoC Synthesis with Automatic Hardware Software Interface Generation. [Citation Graph (0, 0)][DBLP] VLSI Design, 2003, pp:585-0 [Conf]
- M. Balakrishnan, S. Sutarwala, Arun K. Majumdar, Dilip K. Banerji, James G. Linders
A Semantic Approach for Modular Synthesis of VLSI Systems. [Citation Graph (0, 0)][DBLP] Inf. Process. Lett., 1988, v:27, n:1, pp:1-7 [Journal]
- M. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders, Jayanti C. Majithia
Allocation of multiport memories in data path synthesis. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:4, pp:536-540 [Journal]
- Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
An efficient technique for exploring register file size in ASIP design. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1693-1699 [Journal]
- A. R. Naseer, M. Balakrishnan, Anshul Kumar
Direct mapping of RTL structures onto LUT-based FPGA's. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:7, pp:624-631 [Journal]
- Lars Wehmeyer, Manoj Kumar Jain, Stefan Steinke, Peter Marwedel, M. Balakrishnan
Analysis of the influence of register file size on energyconsumption, code size, and execution time. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1329-1337 [Journal]
- M. Balakrishnan, Heman Khanna
Allocation of FIFO structures in RTL data paths. [Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:294-310 [Journal]
- Anup Gangwar, M. Balakrishnan, Anshul Kumar
Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures. [Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:1, pp:- [Journal]
Online cache state dumping for processor debug. [Citation Graph (, )][DBLP]
A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors. [Citation Graph (, )][DBLP]
Cache aware compression for processor debug support. [Citation Graph (, )][DBLP]
A Behavioral Synthesis Approach for Distributed Memory FPGA Architectures. [Citation Graph (, )][DBLP]
Yield Prediction Through Feed Forward Neural Network Approach for Direct Seeded Rice (Oryza sativa) in Bay Islands. [Citation Graph (, )][DBLP]
A framework for energy consumption based design space exploration for wireless sensor nodes. [Citation Graph (, )][DBLP]
An experimental validation of system level design space exploration methodology for energy efficient sensor nodes. [Citation Graph (, )][DBLP]
Clocking-Based Coplanar Wire Crossing Scheme for QCA. [Citation Graph (, )][DBLP]
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