The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Anshul Kumar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar
    Exploring the Number of Register Windows in ASIP Synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:233-238 [Conf]
  2. Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan
    A New Divide and Conquer Method for Achieving High Speed Division in Hardware. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:535-540 [Conf]
  3. Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
    An efficient technique for exploring register file size in ASIP synthesis. [Citation Graph (0, 0)][DBLP]
    CASES, 2002, pp:252-261 [Conf]
  4. Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan
    Automatic synthesis of system on chip multiprocessor architectures for process networks. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:60-65 [Conf]
  5. Kumar Ramayya, Anshul Kumar, Surendra Prasad
    An automated data path synthesizer for a canonic structure, implementable in VLSI. [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:381-387 [Conf]
  6. Anjali Arya, Anshul Kumar, V. V. Swaminathan, Amit Misra
    Automatic generation of digital system schematic diagrams. [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:388-395 [Conf]
  7. Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar
    Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:730-735 [Conf]
  8. Johnny Öberg, Ahmed Hemani, Anshul Kumar
    Scheduling of Outputs in Grammar-based Hardware Synthesis of Data Communication Protocols. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:596-0 [Conf]
  9. Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
    Exploring Storage Organization in ASIP Synthesis. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:120-127 [Conf]
  10. Johnny Öberg, Anshul Kumar, Ahmed Hemani
    Specification of Exception Handling in Grammar-Based Hardware Synthesis. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10038-10041 [Conf]
  11. Sushil Chandra Jain, Anshul Kumar, Shashi Kumar
    Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:201-210 [Conf]
  12. A. R. Naseer, M. Balakrishnan, Anshul Kumar
    An Efficient Technique for Mapping RTL Structures onto FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:99-110 [Conf]
  13. A. R. Naseer, M. Balakrishnan, Anshul Kumar
    Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1995, pp:139-148 [Conf]
  14. Anshul Kumar, P. C. P. Bhatt
    A Structured Language for CAD of Digital Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 1980, pp:308-316 [Conf]
  15. M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha
    A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:2-7 [Conf]
  16. M. Balakrishnan, Anshul Kumar, C. P. Joshi
    A New Performance Evaluation Approach for System Level Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:180-185 [Conf]
  17. Johnny Öberg, Anshul Kumar, Ahmed Hemani
    Grammar-Based Hardware Synthesis of Data Communication Protocols. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:14-19 [Conf]
  18. Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrishnan, Anshul Kumar
    Rapid Resource-Constrained Hardware Performance Estimation. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2006, pp:40-46 [Conf]
  19. Sushil Chandra Jain, Anshul Kumar, Shashi Kumar
    Hybrid Multi-FPGA Board Evaluation by Limiting Multi-Hop Routing. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2002, pp:66-0 [Conf]
  20. Diviya Jain, Anshul Kumar, Laura Pozzi, Paolo Ienne
    Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2004, pp:17-32 [Conf]
  21. Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
    A Novel BIST Architecture With Built-in Self Check. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:57-60 [Conf]
  22. Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
    Efficient Implementation of Multiple On-Chip Signature Checking. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:297-302 [Conf]
  23. Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
    Hybrid Testing Schemes Based on Mutual and Signature Testing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:293-0 [Conf]
  24. Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
    On-Chip Signature Checking for Embedded Memories. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:558-563 [Conf]
  25. C. S. Ajay, M. Balakrishnan, D. Harikrishna, M. Karunakaran, Anshul Kumar, Shashi Kumar, V. Mudgil, A. R. Naseer
    High Level Design Experiences with IDEAS. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:110- [Conf]
  26. Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar
    Exploring the Number of Register Windows in ASIP Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:233-238 [Conf]
  27. Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan
    Synthesis of Application Specific Multiprocessor Architectures for Process Networks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:780-783 [Conf]
  28. Ram Lakhan Gupta, Anshul Kumar, Aalbert Van Der Werf, Natalino G. Busa
    Synthesizing A Long Latency Unit Within Vliw Processor. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:460-0 [Conf]
  29. Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
    ASIP Design Methodologies : Survey and Issues. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:76-0 [Conf]
  30. Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
    Integrated On-Chip Storage Evaluation in ASIP Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:274-279 [Conf]
  31. Sitanshu Jain, M. Balakrishnan, Anshul Kumar, Shashi Kumar
    Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:400-405 [Conf]
  32. Sushil Chandra Jain, Shashi Kumar, Anshul Kumar
    Evaluation of Various Routing Architectures for Multi-FPGA Boards. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:262-267 [Conf]
  33. Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van Eijndhoven, Anshul Kumar
    Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:177-182 [Conf]
  34. Alok Kumar, Anshul Kumar, M. Balakrishnan
    Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:75-80 [Conf]
  35. Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan
    A New Divide and Conquer Method for Achieving High Speed Division in Hardware. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:535-540 [Conf]
  36. A. R. Naseer, M. Balakrishnan, Anshul Kumar
    FAST: FPGA Targeted RTL Structure Synthesis Technique. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:21-24 [Conf]
  37. A. R. Naseer, M. Balakrishnan, Anshul Kumar
    Optimal Clock Period for Synthesized Data Paths. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:134-139 [Conf]
  38. Johnny Öberg, Axel Jantsch, Anshul Kumar
    An Object-Oriented Concept for Intelligent Library Functions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:355-358 [Conf]
  39. Arvind Rajawat, M. Balakrishnan, Anshul Kumar
    nterface Synthesis: Issues and Approaches. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:92- [Conf]
  40. M. V. Rao, M. Balakrishnan, Anshul Kumar
    DESSERT: Design Space Exploration of RT Level Components. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:299-304 [Conf]
  41. Venkat Rao, Gaurav Singhal, Anshul Kumar
    Real Time Dynamic Voltage Scaling For Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:650-653 [Conf]
  42. Venkat Rao, Gaurav Singhal, Anshul Kumar, Nicolas Navet
    Battery Model for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:105-110 [Conf]
  43. Anupam Rastogi, M. Balakrishnan, Anshul Kumar
    Integrating Communication Cost Estimation in Embedded Systems Design : A PCI Case Study. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:23-28 [Conf]
  44. Sourabh Saluja, Anshul Kumar
    Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:761-764 [Conf]
  45. Amarjeet Singh 0002, Amit Chhabra, Anup Gangwar, Basant Kumar Dwivedi, M. Balakrishnan, Anshul Kumar
    SoC Synthesis with Automatic Hardware Software Interface Generation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:585-0 [Conf]
  46. B. M. Subraya, Anshul Kumar, Shashi Kumar
    An HOL based framework for design of correct high level synthesizers. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:249-254 [Conf]
  47. Nagaraju Pothineni, Anshul Kumar, Kolin Paul
    Application Specific Datapath Extension with Distributed I/O Functional Units. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:551-558 [Conf]
  48. Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda
    Power Reduction in VLIW Processor with Compiler Driven Bypass Network. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:233-238 [Conf]
  49. Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
    An efficient technique for exploring register file size in ASIP design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1693-1699 [Journal]
  50. A. R. Naseer, M. Balakrishnan, Anshul Kumar
    Direct mapping of RTL structures onto LUT-based FPGA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:7, pp:624-631 [Journal]
  51. Anup Gangwar, M. Balakrishnan, Anshul Kumar
    Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:1, pp:- [Journal]

  52. Recurring Pattern Identification and its Application to Instruction Set Extension. [Citation Graph (, )][DBLP]


  53. A scheme for multiple on-chip signature checking for embedded SRAMs. [Citation Graph (, )][DBLP]


  54. A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions. [Citation Graph (, )][DBLP]


  55. Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors. [Citation Graph (, )][DBLP]


  56. Instruction Selection in ASIP Synthesis Using Functional Matching. [Citation Graph (, )][DBLP]


  57. Front-End Design Flows for Systems on Chip: An Embedded Tutorial. [Citation Graph (, )][DBLP]


  58. An Index-Based Mobile Checkpointing and Recovery Algorithm. [Citation Graph (, )][DBLP]


Search in 0.023secs, Finished in 0.026secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002