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Title:
Author:
Massoud Pedram: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
    Parameterized block-based non-gaussian statistical gate timing analysis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:947-952 [Conf]
  2. Soroush Abbaspour, Massoud Pedram
    Gate delay calculation considering the crosstalk capacitances. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:852-857 [Conf]
  3. Amir H. Ajami, Massoud Pedram
    Post-layout timing-driven cell placement using an accurate net length model with movable Steiner points. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:595-600 [Conf]
  4. Wei Chen, Massoud Pedram, Premal Buch
    Buffered Routing Tree Construction Under Buffer Placement Blockages. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:381-386 [Conf]
  5. Wei-Chung Cheng, Jian-Lin Liang, Massoud Pedram
    Software-Only Bus Encoding Techniques for an Embedded System. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:126-131 [Conf]
  6. Wei-Chung Cheng, Massoud Pedram
    Low power techniques for address encoding and memory allocation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:245-250 [Conf]
  7. Payam Heydari, Massoud Pedram
    Balanced truncation with spectral shaping for RLC interconnects. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:203-208 [Conf]
  8. Payam Heydari, Massoud Pedram
    Interconnect Energy Dissipation in High-Speed ULSI Circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:132-140 [Conf]
  9. Chanseok Hwang, Massoud Pedram
    Interconnect design methods for memory design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:438-443 [Conf]
  10. Chanseok Hwang, Massoud Pedram
    PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:428-431 [Conf]
  11. Chanseok Hwang, Massoud Pedram
    Timing-driven placement based on monotone cell ordering constraints. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:201-206 [Conf]
  12. Chang Woo Kang, Ali Iranli, Massoud Pedram
    Technology mapping and packing for coarse-grained, anti-fuse based FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:209-211 [Conf]
  13. Chang Woo Kang, Massoud Pedram
    Clustering techniques for coarse-grained, antifuse FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:785-790 [Conf]
  14. Jinan Lou, Amir H. Salek, Massoud Pedram
    An Integrated Flow for Technology Remapping and Placement of Sub-half-micron Circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:295-300 [Conf]
  15. Jaewon Oh, Massoud Pedram
    Power Reduction in Microprocessor Chips by Gated Clock Routing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:313-318 [Conf]
  16. Shihliang Ou, Massoud Pedram
    Timing-Driven Bipartitioning with Replication Using Iterative Quadratic Programming. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:105-108 [Conf]
  17. Massoud Pedram, Xunwei Wu
    Analysis of power-clocked CMOS with application to the design of energy-recovery circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:339-344 [Conf]
  18. Massoud Pedram, Chi-Ying Tsui, Qing Wu
    An Integrated Battery-Hardware Model for Portable Electronics. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:109-0 [Conf]
  19. Shahin Nazarian, Massoud Pedram, Tao Lin, Emre Tuncer
    CGTA: current gain-based timing analysis for logic cells. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:67-72 [Conf]
  20. Massoud Pedram, Qing Wu, Xunwei Wu
    A New Design for Double Edge Triggered Flip-flops. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:417-421 [Conf]
  21. Payam Rabiei, Massoud Pedram
    Model Order Reduction of Large Circuits Using Balanced Truncation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:237-0 [Conf]
  22. Peng Rong, Massoud Pedram
    Power-aware scheduling and dynamic voltage setting for tasks running on a hard real-time system. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:473-478 [Conf]
  23. Massoud Pedram
    Power optimization and management in embedded systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:239-244 [Conf]
  24. Massoud Pedram
    Logical-Physical Co-design for Deep Submicron Circuits: Challenges and Solutions (Embedded Tutorial). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:137-142 [Conf]
  25. Hojun Shim, Naehyuck Chang, Massoud Pedram
    A compressed frame buffer to reduce display power consumption in mobile systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:818-823 [Conf]
  26. Qing Wu, Qinru Qiu, Massoud Pedram
    An interleaved dual-battery power supply for battery-operated electronics. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:387-390 [Conf]
  27. Xunwei Wu, Jian Wei, Massoud Pedram, Qing Wu
    Low-power design of sequential circuits using a quasi-synchronous derived clock. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:345-350 [Conf]
  28. Wonbok Lee, Kimish Patel, Massoud Pedram
    B2Sim: : a fast micro-architecture simulator based on basic block characterization. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:199-204 [Conf]
  29. Afshin Abdollahi, Farzan Fallah, Massoud Pedram
    An effective power mode transition technique in MTCMOS circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:37-42 [Conf]
  30. Afshin Abdollahi, Massoud Pedram
    A new canonical form for fast boolean matching in logic synthesis and verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:379-384 [Conf]
  31. Amir H. Ajami, Kaustav Banerjee, Massoud Pedram, Lukas P. P. P. van Ginneken
    Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:567-572 [Conf]
  32. Jui-Ming Chang, Massoud Pedram
    Register Allocation and Binding for Low Power. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:29-35 [Conf]
  33. Kamal Chaudhary, Massoud Pedram
    A Near Optimal Algorithm for Technology Mapping Minimizing Area under Delay Constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:492-498 [Conf]
  34. Kihwan Choi, Ramakrishna Soma, Massoud Pedram
    Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:544-549 [Conf]
  35. Kihwan Choi, Kwanho Kim, Massoud Pedram
    Energy-aware MPEG-4 FGS streaming. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:912-915 [Conf]
  36. Chih-Shun Ding, Qing Wu, Cheng-Ta Hsieh, Massoud Pedram
    Statistical Estimation of the Cumulative Distribution Function for Power Dissipation in VLSI Cirucits. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:371-376 [Conf]
  37. Hanif Fatemi, Shahin Nazarian, Massoud Pedram
    Statistical logic cell delay analysis using a current-based model. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:253-256 [Conf]
  38. Cheng-Ta Hsieh, Massoud Pedram, Gaurav Mehta, Fred Rastgar
    Profile-Driven Program Synthesis for Evaluation of System Power Dissipation. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:576-581 [Conf]
  39. Sasan Iman, Massoud Pedram
    Logic Extraction and Factorization for Low Power. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:248-253 [Conf]
  40. Sasan Iman, Massoud Pedram
    POSE: Power Optimization and Synthesis Environment. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:21-26 [Conf]
  41. Sasan Iman, Massoud Pedram, Kamal Chaudhary
    Technology Mapping Using Fuzzy Logic. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:333-338 [Conf]
  42. Ali Iranli, Wonbok Lee, Massoud Pedram
    Backlight dimming in power-aware mobile displays. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:604-607 [Conf]
  43. Ali Iranli, Massoud Pedram
    DTM: dynamic tone mapping for backlight scaling. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:612-617 [Conf]
  44. Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula
    BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:642-647 [Conf]
  45. Enrico Macii, Massoud Pedram, Fabio Somenzi
    High-Level Power Modeling, Estimation, and Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:504-511 [Conf]
  46. Shihming Liu, Massoud Pedram, Alvin M. Despain
    A Fast State Assignment Procedure for Large FSMs. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:327-332 [Conf]
  47. Jaewon Oh, Massoud Pedram
    Multi-Pad Power/Ground Network Design for Uniform Distribution of Ground Bounce. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:287-290 [Conf]
  48. Shih-Lian T. Ou, Massoud Pedram
    Timing-driven placement based on partitioning with dynamic cut-net control. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:472-476 [Conf]
  49. Radu Marculescu, Diana Marculescu, Massoud Pedram
    Efficient Power Estimation for Highly Correlated Input Streams. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:628-634 [Conf]
  50. Diana Marculescu, Radu Marculescu, Massoud Pedram
    Stochastic Sequential Machine Synthesis Targeting Constrained Sequence Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:696-701 [Conf]
  51. Diana Marculescu, Radu Marculescu, Massoud Pedram
    Sequence Compaction for Probabilistic Analysis of Finite-State Machines. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:12-15 [Conf]
  52. Radu Marculescu, Diana Marculescu, Massoud Pedram
    Hierarchical Sequence Compaction for Power Estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:570-575 [Conf]
  53. Jaewon Oh, Iksoo Pyo, Massoud Pedram
    Constructing Lower and Upper Bounded Delay Routing Trees Using Linear Programming. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:401-404 [Conf]
  54. Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram
    Charge recycling in MTCMOS circuits: concept and analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:97-102 [Conf]
  55. Massoud Pedram, Narasimha B. Bhat
    Layout Driven Technology Mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:99-105 [Conf]
  56. Massoud Pedram, Qing Wu
    Design Considerations for Battery-Powered Electronics. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:861-866 [Conf]
  57. Bryan Preas, Massoud Pedram, D. Curry
    Automatic Layout of Silicon-on-Silicon Hybrid Packages. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:394-399 [Conf]
  58. Qinru Qiu, Massoud Pedram
    Dynamic Power Management Based on Continuous-Time Markov Decision Processes. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:555-561 [Conf]
  59. Qinru Qiu, Qing Wu, Massoud Pedram
    Dynamic power management of complex systems using generalized stochastic Petri nets. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:352-356 [Conf]
  60. Qinru Qiu, Qing Wu, Massoud Pedram
    Dynamic Power Management in a Mobile Multimedia System with Guaranteed Quality-of-Service. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:834-839 [Conf]
  61. Qinru Qiu, Qing Wu, Massoud Pedram
    Maximum Power Estimation Using the Limiting Distributions of Extreme Order Statistics. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:684-689 [Conf]
  62. Peng Rong, Massoud Pedram
    Extending the lifetime of a network of battery-powered mobile devices by remote processing: a markovian decision-based approach. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:906-911 [Conf]
  63. Amir H. Salek, Jinan Lou, Massoud Pedram
    A DSM Design Flow: Putting Floorplanning, Technology-Napping, and Gate-Placement Together. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:128-134 [Conf]
  64. Amir H. Salek, Jinan Lou, Massoud Pedram
    MERLIN: Semi-Order-Independent Hierarchical Buffered Routing Tree Generation Using Local Neighborhood Search. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:472-478 [Conf]
  65. Chi-Ying Tsui, Kai-Keung Chan, Qing Wu, Chih-Shun Ding, Massoud Pedram
    A Power Estimation Framework for Designing Low Power Portable Video Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:421-424 [Conf]
  66. Chi-Ying Tsui, Radu Marculescu, Diana Marculescu, Massoud Pedram
    Improving the Efficiency of Power Simulators by Input Vector Compaction. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:165-168 [Conf]
  67. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
    Technology Decomposition and Mapping Targeting Low Power Dissipation. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:68-73 [Conf]
  68. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
    Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:18-23 [Conf]
  69. Hirendu Vaishnav, Massoud Pedram
    Routability-Driven Fanout Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:230-235 [Conf]
  70. Hirendu Vaishnav, Massoud Pedram
    Minimizing the Routing Cost During Logic Extraction. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:70-75 [Conf]
  71. Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
    Non-gaussian statistical interconnect timing analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:533-538 [Conf]
  72. Afshin Abdollahi, Massoud Pedram
    Analysis and synthesis of quantum circuits by using quantum decision diagrams. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:317-322 [Conf]
  73. Yazdan Aghaghiri, Massoud Pedram, Farzan Fallah
    EZ Encoding: A Class of Irredundant Low Power Codes for Data Address and Multiplexed Address Buses. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1102- [Conf]
  74. Behnam Amelifard, Farzan Fallah, Massoud Pedram
    Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:995-1000 [Conf]
  75. Jaewon Oh, Massoud Pedram
    Gated Clock Routing Minimizing the Switched Capacitance. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:692-697 [Conf]
  76. Kihwan Choi, Ramakrishna Soma, Massoud Pedram
    Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Trade-Off Based on the Ratio of Off-Chip Access to On-Chip Computation Times. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:4-9 [Conf]
  77. Jui-Ming Chang, Massoud Pedram
    Codex-dp: Co-design of Communicating Systems Using Dynamic Programming. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:568-0 [Conf]
  78. Wei-Chung Cheng, Yu Hou, Massoud Pedram
    Power Minimization in a Backlit TFT-LCD Display by Concurrent Brightness and Contrast Scaling. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:252-259 [Conf]
  79. Wei-Chung Cheng, Massoud Pedram
    Chromatic Encoding: A Low Power Encoding Technique for Digital Visual Interface. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10694-10699 [Conf]
  80. Cheng-Ta Hsieh, L. Chen, Massoud Pedram
    Microprocessor power analysis by labeled simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:182-189 [Conf]
  81. Cheng-Ta Hsieh, Massoud Pedram
    Architectural Power Optimization by Bus Splitting. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:612-611 [Conf]
  82. Ali Iranli, Kihwan Choi, Massoud Pedram
    A Game Theoretic Approach to Low Energy Wireless Video Streaming. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:696-697 [Conf]
  83. Ali Iranli, Hanif Fatemi, Massoud Pedram
    HEBS: Histogram Equalization for Backlight Scaling. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:346-351 [Conf]
  84. Enrico Macii, Massoud Pedram, Dirk Friebel, Robert C. Aitken, Antun Domic, Roberto Zafalon
    Low-power design tools: are EDA vendors taking this matter seriously? [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1227- [Conf]
  85. Diana Marculescu, Radu Marculescu, Massoud Pedram
    Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:774-0 [Conf]
  86. Radu Marculescu, Massoud Pedram, Jörg Henkel
    Distributed Multimedia System Design: A Holistic Perspective. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1342-1349 [Conf]
  87. Shahin Nazarian, Massoud Pedram
    Cell delay analysis based on rate-of-current change. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:539-544 [Conf]
  88. Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta, Melvin A. Breuer
    STAX: statistical crosstalk target set compaction. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:172-177 [Conf]
  89. Shahin Nazarian, Massoud Pedram, Emre Tuncer, Tao Lin, Amir H. Ajami
    Modeling and Propagation of Noisy Waveforms in Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:776-777 [Conf]
  90. Massoud Pedram, Qing Wu
    Battery-Powered Digital CMOS Design. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:72-76 [Conf]
  91. Peyman Rezvani, Massoud Pedram
    Concurrent and Selective Logic Extraction with Timing Consideration. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1086- [Conf]
  92. Peng Rong, Massoud Pedram
    An Analytical Model for Predicting the Remaining Battery Capacity of Lithium-Ion Batteries. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11148-11149 [Conf]
  93. Peng Rong, Massoud Pedram
    Determining the optimal timeout values for a power-managed system based on the theory of Markovian processes: offline and online algorithms. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1128-1133 [Conf]
  94. Ali Iranli, Kihwan Choi, Massoud Pedram
    Energy-Aware Wireless Video Streaming. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2003, pp:48-55 [Conf]
  95. Soroush Abbaspour, Amir H. Ajami, Massoud Pedram, Emre Tuncer
    TFA: a threshold-based filtering algorithm for propagation delay and slew calculation of high-speed VLSI interconnects. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:19-24 [Conf]
  96. Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
    VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:426-430 [Conf]
  97. Hanif Fatemi, Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Emre Tuncer
    SACI: statistical static timing analysis of coupled interconnects. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:241-246 [Conf]
  98. Chang Woo Kang, Soroush Abbaspour, Massoud Pedram
    Buffer sizing for minimum energy-delay product by using an approximating polynomial. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:112-115 [Conf]
  99. Chang Woo Kang, Massoud Pedram
    Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:79-84 [Conf]
  100. Shahin Nazarian, Ali Iranli, Massoud Pedram
    Crosstalk analysis in nanometer technologies. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:253-258 [Conf]
  101. Shahin Nazarian, Massoud Pedram, Emre Tuncer
    An empirical study of crosstalk in VDSM technologies. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:317-322 [Conf]
  102. Chanseok Hwang, Peng Rong, Massoud Pedram
    Sleep transistor distribution in row-based MTCMOS designs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:235-240 [Conf]
  103. Kimish Patel, Wonbok Lee, Massoud Pedram
    Active bank switching for temperature control of the register file in a microprocessor. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:231-234 [Conf]
  104. Amir H. Ajami, Kaustav Banerjee, Massoud Pedram
    Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:44-48 [Conf]
  105. Wei Chen, Cheng-Ta Hsieh, Massoud Pedram
    Simultaneous Gate Sizing and Fanout Optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:374-378 [Conf]
  106. Kihwan Choi, Karthik Dantu, Wei-Chung Cheng, Massoud Pedram
    Frame-based dynamic voltage and frequency scaling for a MPEG decoder. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:732-737 [Conf]
  107. Kihwan Choi, Wonbok Lee, Ramakrishna Soma, Massoud Pedram
    Dynamic voltage and frequency scaling under a precise energy model considering variable and fixed components of the system power dissipation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:29-34 [Conf]
  108. Pasquale Cocchini, Massoud Pedram, Gianluca Piccinini, Maurizio Zamboni
    Fanout optimization under a submicron transistor-level delay model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:551-556 [Conf]
  109. Chih-Shun Ding, Cheng-Ta Hsieh, Qing Wu, Massoud Pedram
    Stratified random sampling for power estimation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:576-582 [Conf]
  110. Payam Heydari, Massoud Pedram
    Model Reduction of Variable-Geometry Interconnects using Variational Spectrally-Weighted Balanced Truncation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:586-591 [Conf]
  111. Cheng-Ta Hsieh, Qing Wu, Chih-Shun Ding, Massoud Pedram
    Statistical sampling and regression analysis for RT-level power evaluation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:583-588 [Conf]
  112. Sasan Iman, Massoud Pedram
    Multi-level network optimization for low power. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:372-377 [Conf]
  113. Sasan Iman, Massoud Pedram
    Two-level logic minimization for low power. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:433-438 [Conf]
  114. Ali Iranli, Hanif Fatemi, Massoud Pedram
    A Game Theoretic Approach to Dynamic Energy Minimization in Wireless Transceivers. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:504-509 [Conf]
  115. Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula
    FGILP: an integer linear program solver based on function graphs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:685-689 [Conf]
  116. Jinan Lou, Wei Chen, Massoud Pedram
    Concurrent logic restructuring and placement for timing closure. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:31-36 [Conf]
  117. Jinan Lou, Amir H. Salek, Massoud Pedram
    An exact solution to simultaneous technology mapping and linear placement problem. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:671-675 [Conf]
  118. Radu Marculescu, Diana Marculescu, Massoud Pedram
    Switching activity analysis considering spatiotemporal correlations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:294-299 [Conf]
  119. Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer
    Merging multiple FSM controllers for DFT/BIST hardware. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:720-725 [Conf]
  120. Massoud Pedram, Narasimha B. Bhat
    Layout Driven Logic Restructuring/Decomposition. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:134-137 [Conf]
  121. Massoud Pedram, Malgorzata Marek-Sadowska, Ernest S. Kuh
    Floorplanning with Pin Assignment. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:98-101 [Conf]
  122. Massoud Pedram, Bahman S. Nobandegani, Bryan Preas
    Architecture and routability analysis for row-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:230-235 [Conf]
  123. Peyman Rezvani, Amir H. Ajami, Massoud Pedram, Hamid Savoj
    LEOPARD: a Logical Effort-based fanout OPtimizer for ARea and Delay. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:516-519 [Conf]
  124. Peng Rong, Massoud Pedram
    Battery-aware power management based on Markovian decision processes. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:707-713 [Conf]
  125. Amir H. Salek, Jinan Lou, Massoud Pedram
    A simultaneous routing tree construction and fanout optimization algorithm. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:625-630 [Conf]
  126. Chi-Ying Tsui, Massoud Pedram, Chih-Ang Chen, Alvin M. Despain
    Low power state assignment targeting two-and multi-level logic implementations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:82-87 [Conf]
  127. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
    Efficient estimation of dynamic power consumption under a real delay model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:224-228 [Conf]
  128. Hirendu Vaishnav, Massoud Pedram
    Delay optimal partitioning targeting low power VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:638-643 [Conf]
  129. Mehrdad Najibi, M. Salehi, Ali Afzali-Kusha, Massoud Pedram, Seid Mehdi Fakhraie, Hossein Pedram
    Dynamic voltage and frequency management based on variable update intervals for frequency setting. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:755-760 [Conf]
  130. Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
    VGTA: Variation Aware Gate Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:351-356 [Conf]
  131. Afshin Abdollahi, Massoud Pedram, Farzan Fallah, Indradeep Ghosh
    Precomputation-based Guarding for Dynamic and Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:90-97 [Conf]
  132. Farhad Ghasemi-Tari, Peng Rong, Massoud Pedram
    An Energy-Aware Simulation Model and Transaction Protocol for Dynamic Workload Distribution in Mobile Ad Hoc Networks. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:444-0 [Conf]
  133. Payam Heydari, Massoud Pedram
    Analysis and Optimization of Ground Bounce in Digital CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:121-126 [Conf]
  134. Payam Heydari, Massoud Pedram
    Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:104-109 [Conf]
  135. Payam Heydari, Massoud Pedram
    Jitter-Induced Power/ground Noise in CMOS PLLs: A Design Perspective. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:209-213 [Conf]
  136. Yung-Te Lai, Kuo-Rueih Ricky Pan, Massoud Pedram
    FPGA Synthesis Using Function Decomposition. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:30-35 [Conf]
  137. Yung-Te Lai, Sarma Sastry, Massoud Pedram
    Boolean Matching Using Binary Decision Diagrams with Applications to Logic Synthesis and Verification. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:452-458 [Conf]
  138. Rakesh Mehrotra, Massoud Pedram, Xunwei Wu
    Comparison between nMos Pass Transistor logic style vs. CMOS Complementary Cells. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:130-135 [Conf]
  139. Massoud Pedram, Kamal Chaudhary, Ernest S. Kuh
    I/O Pad Assignment Based on the Circuit Structure. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:314-318 [Conf]
  140. Hirendu Vaishnav, Chi-Keung Lee, Massoud Pedram
    Post Layout Speed-up by Event Elimination. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:211-216 [Conf]
  141. Hirendu Vaishnav, Massoud Pedram
    Logic extraction based on normalized netlengths. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:658-663 [Conf]
  142. Morteza Maleki, Massoud Pedram
    QoM and lifetime-constrained random deployment of sensor networks for minimum energy consumption. [Citation Graph (0, 0)][DBLP]
    IPSN, 2005, pp:293-300 [Conf]
  143. Ali Iranli, Hanif Fatemi, Massoud Pedram
    Lifetime-aware intrusion detection under safeguarding constraints. [Citation Graph (0, 0)][DBLP]
    IPSN, 2005, pp:189-194 [Conf]
  144. Shihming Liu, Massoud Pedram, Alvin M. Despain
    PLATO P: PLA Timing Optimization by Partitioning. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1744-1747 [Conf]
  145. Afshin Abdollahi, Massoud Pedram, Farzan Fallah
    Runtime mechanisms for leakage current reduction in CMOS VLSI circuits1, 2. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:213-218 [Conf]
  146. Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram
    Irredundant address bus encoding for low power. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:182-187 [Conf]
  147. Yazdan Aghaghiri, Massoud Pedram, Farzan Fallah
    Reducing transitions on memory buses using sector-based encoding technique. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:190-195 [Conf]
  148. Behnam Amelifard, Farzan Fallah, Massoud Pedram
    Low-power fanout optimization using multiple threshold voltage inverters. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:95-98 [Conf]
  149. Jui-Ming Chang, Massoud Pedram
    Energy minimization using multiple supply voltages. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:157-162 [Conf]
  150. Xunwei Wu, Massoud Pedram
    Low power sequential circuit design by using priority encoding and clock gating. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:143-148 [Conf]
  151. Wei-Chung Cheng, Massoud Pedram
    Power-optimal encoding for DRAM address bus (poster session). [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:250-252 [Conf]
  152. Kihwan Choi, Ramakrishna Soma, Massoud Pedram
    Dynamic voltage and frequency scaling based on workload decomposition. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:174-179 [Conf]
  153. Chih-Shun Ding, Cheng-Ta Hsieh, Massoud Pedram
    Improving sampling efficiency for system level power estimation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:115-117 [Conf]
  154. Ali Iranli, Morteza Maleki, Massoud Pedram
    Energy efficient strategies for deployment of a two-level wireless sensor network. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:233-238 [Conf]
  155. Morteza Maleki, Karthik Dantu, Massoud Pedram
    Power-aware source routing protocol for mobile ad hoc networks. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:72-75 [Conf]
  156. Diana Marculescu, Radu Marculescu, Massoud Pedram
    Information theoretic measures of energy consumption at register transfer level. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:81-86 [Conf]
  157. Radu Marculescu, Diana Marculescu, Massoud Pedram
    Composite sequence compaction for finite-state machines using block entropy and high-order Markov models. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:190-195 [Conf]
  158. Diana Marculescu, Radu Marculescu, Massoud Pedram
    Theoretical bounds for switching activity analysis in finite-state machines. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:36-41 [Conf]
  159. Radu Marculescu, Diana Marculescu, Massoud Pedram
    Non-stationary effects in trace-driven power analysis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:133-138 [Conf]
  160. Qinru Qiu, Qing Wu, Massoud Pedram
    Stochastic modeling of a power-managed system: construction and optimization. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:194-199 [Conf]
  161. Qinru Qiu, Qing Wu, Massoud Pedram, Chih-Shun Ding
    Cycle-accurate macro-models for RT-level power analysis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:125-130 [Conf]
  162. Peng Rong, Massoud Pedram
    Hierarchical power management with application to scheduling. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:269-274 [Conf]
  163. Behnam Amelifard, Farzan Fallah, Massoud Pedram
    Low-power fanout optimization using MTCMOS and multi-Vt techniques. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:334-337 [Conf]
  164. Wonbok Lee, Kimish Patel, Massoud Pedram
    Dynamic thermal management for MPEG-2 decoding. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:316-321 [Conf]
  165. Xunwei Wu, Massoud Pedram
    Propagation Algorithm of Behavior Probability in Power Estimation Based on Multiple-Valued Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:453-459 [Conf]
  166. Xunwei Wu, Massoud Pedram
    Design of Ternary CCD Circuits Referencing to Current-Mode CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1997, pp:209-214 [Conf]
  167. Kaustav Banerjee, Massoud Pedram, Amir H. Ajami
    Analysis and optimization of thermal issues in high-performance VLSI. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:230-237 [Conf]
  168. Payam Heydari, Massoud Pedram
    Calculation of ramp response of lossy transmission lines using two-port network functions. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:152-157 [Conf]
  169. Wei Chen, Cheng-Ta Hsieh, Massoud Pedram
    Gate sizing with controlled displacement. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:127-132 [Conf]
  170. Soroush Abbaspour, Massoud Pedram, Payam Heydari
    Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line Drivers. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:261-266 [Conf]
  171. Afshin Abdollahi, Farzan Fallah, Massoud Pedram
    Leakage Current Reduction in Sequential Circuits by Modifying the Scan Chains. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:49-54 [Conf]
  172. Afshin Abdollahi, Farzan Fallah, Massoud Pedram
    Analysis and Optimization of Static Power Considering Transition Dependency of Leakage Current in VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:77-82 [Conf]
  173. Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram
    ALBORZ: Address Level Bus Power Optimization. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:470-0 [Conf]
  174. Behnam Amelifard, Farzan Fallah, Massoud Pedram
    Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-Power High-Performance Adders. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:148-152 [Conf]
  175. Behnam Amelifard, Massoud Pedram, Farzan Fallah
    Low-leakage SRAM Design with Dual V_t Transistors. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:729-734 [Conf]
  176. Wei-Chung Cheng, Massoud Pedram
    Memory Bus Encoding for Low Power: A Tutorial. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:199-204 [Conf]
  177. Chanseok Hwang, Chang Woo Kang, Massoud Pedram
    Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:741-746 [Conf]
  178. Shahin Nazarian, Massoud Pedram, Emre Tuncer, Tao Lin
    Sensitivity-Based Gate Delay Propagation in Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:536-541 [Conf]
  179. Hwisung Jung, Massoud Pedram
    A Unified Framework for System-Level Design: Modeling and Performance Optimization of Scalable Networking Systems. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:198-203 [Conf]
  180. Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer
    Control Strategies for Chip-Based DFT/BIST Hardware. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:893-902 [Conf]
  181. Chang Woo Kang, Massoud Pedram
    Technology Mapping for Low Leakage Power with Hot-Carrier Effect Consideration. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:295-300 [Conf]
  182. Stefan Mayrhofer, Massoud Pedram, Ulrich Lauther
    A Flow-Oriented Approach to the Placement of Boolean Networks. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:101-110 [Conf]
  183. Wei Chen, Massoud Pedram, Premal Buch
    Buffered Routing Tree Construction under Buffer Placement Blockages. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:381-386 [Conf]
  184. Wei-Chung Cheng, Jian-Lin Liang, Massoud Pedram
    Software-Only Bus Encoding Techniques for an Embedded System. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:126-131 [Conf]
  185. Payam Heydari, Massoud Pedram
    Interconnect Energy Dissipation in High-Speed ULSI Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:132-0 [Conf]
  186. Hojun Shim, Naehyuck Chang, Massoud Pedram
    A Backlight Power Management Framework for Battery-Operated Multimedia Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:5, pp:388-396 [Journal]
  187. Paul Tafertshofer, Massoud Pedram
    Factored Edge-Valued Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1997, v:10, n:2/3, pp:243-270 [Journal]
  188. Shihming Liu, Massoud Pedram, Alvin M. Despain
    State assignment based on two-dimensional placement and hypercube mapping. [Citation Graph (0, 0)][DBLP]
    Integration, 1997, v:24, n:2, pp:101-118 [Journal]
  189. Jaewon Oh, Iksoo Pyo, Massoud Pedram
    Constructing minimal spanning/Steiner trees with bounded path length. [Citation Graph (0, 0)][DBLP]
    Integration, 1997, v:22, n:1-2, pp:137-163 [Journal]
  190. Chi-Ying Tsui, Massoud Pedram
    Accurate and efficient power simulation strategy by compacting the input vector set. [Citation Graph (0, 0)][DBLP]
    Integration, 1998, v:25, n:1, pp:37-52 [Journal]
  191. Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram
    A Class of Irredundant Encoding Techniques for Reducing Bus Power. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:5, pp:445-458 [Journal]
  192. Wei-Chung Cheng, Massoud Pedram
    Power-Aware Bus Encoding Techniques for I/O and Data Buses in an Embedded System. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:4, pp:351-364 [Journal]
  193. Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula
    Formal Verification Using Edge-Valued Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:2, pp:247-255 [Journal]
  194. Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram
    Transition reduction in memory buses using sector-based encoding techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1164-1174 [Journal]
  195. Amir H. Ajami, Kaustav Banerjee, Massoud Pedram
    Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:849-861 [Journal]
  196. Raul Camposano, Massoud Pedram
    Electronic design automation at the turn of the century: accomplishments and vision of the future. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:12, pp:1401-1403 [Journal]
  197. Jui-Ming Chang, Massoud Pedram
    Codex-dp: co-design of communicating systems using dynamicprogramming. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:732-744 [Journal]
  198. Kamal Chaudhary, Massoud Pedram
    Computing the area versus delay trade-off curves in technology mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1480-1489 [Journal]
  199. Wei Chen, Cheng-Ta Hsieh, Massoud Pedram
    Simultaneous gate sizing and placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:206-214 [Journal]
  200. Kihwan Choi, Ramakrishna Soma, Massoud Pedram
    Fine-grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off-chip access to on-chip computation times. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:18-28 [Journal]
  201. Pasquale Cocchini, Massoud Pedram
    Fanout optimization using bipolar LT-trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:3, pp:339-349 [Journal]
  202. Chih-Shun Ding, Chi-Ying Tsui, Massoud Pedram
    Gate-level power estimation using tagged probabilistic simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1099-1107 [Journal]
  203. Chih-Shun Ding, Qing Wu, Cheng-Ta Hsieh, Massoud Pedram
    Stratified random sampling for power estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:6, pp:465-471 [Journal]
  204. Payam Heydari, Massoud Pedram
    Capacitive coupling noise in high-speed VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:478-488 [Journal]
  205. Cheng-Ta Hsieh, Massoud Pedram
    Architectural energy optimization by bus splitting. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:408-414 [Journal]
  206. Cheng-Ta Hsieh, Massoud Pedram
    Microprocessor power estimation using profile-driven program synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1080-1089 [Journal]
  207. Sasan Iman, Massoud Pedram
    An approach for multilevel logic optimization targeting low power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:889-901 [Journal]
  208. Yung-Te Lai, Kuo-Rueih Ricky Pan, Massoud Pedram
    OBDD-based function decomposition: algorithms and implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:8, pp:977-990 [Journal]
  209. Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula
    EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:8, pp:959-975 [Journal]
  210. Enrico Macii, Massoud Pedram, Fabio Somenzi
    High-level power modeling, estimation, and optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1061-1079 [Journal]
  211. Diana Marculescu, Radu Marculescu, Massoud Pedram
    Information theoretic measures for power analysis [logic design]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:6, pp:599-610 [Journal]
  212. Radu Marculescu, Diana Marculescu, Massoud Pedram
    Probabilistic modeling of dependencies during switching activity analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:2, pp:73-83 [Journal]
  213. Radu Marculescu, Diana Marculescu, Massoud Pedram
    Sequence compaction for power estimation: theory and practice. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:973-993 [Journal]
  214. Jaewon Oh, Massoud Pedram
    Gated clock routing for low-power microprocessor design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:715-722 [Journal]
  215. Massoud Pedram, Bahman S. Nobandegani, Bryan Preas
    Design and analysis of segmented routing channels for row-based FPGA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1470-1479 [Journal]
  216. Massoud Pedram, Sasan Iman
    Correction to "An Approach for Multilevel Logic Optimization Targeting Low Power". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1176- [Journal]
  217. Massoud Pedram, Bryan Preas
    Interconnection analysis for standard cell layouts. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1512-1519 [Journal]
  218. Qinru Qiu, Q. Qu, Massoud Pedram
    Stochastic modeling of a power-managed system-construction andoptimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1200-1217 [Journal]
  219. Peyman Rezvani, Massoud Pedram
    A fanout optimization algorithm based on the effort delay model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:12, pp:1671-1678 [Journal]
  220. Amir H. Salek, Jinan Lou, Massoud Pedram
    An integrated logical and physical design flow for deep submicron circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1305-1315 [Journal]
  221. Peng Rong, Massoud Pedram
    Battery-aware power management based on Markovian decision processes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1337-1349 [Journal]
  222. Amir H. Salek, Jinan Lou, Massoud Pedram
    Hierarchical buffered routing tree generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:554-567 [Journal]
  223. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
    Power efficient technology decomposition and mapping under an extended power consumption model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1110-1122 [Journal]
  224. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
    Low-power state assignment targeting two- and multilevel logic implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1281-1291 [Journal]
  225. Hirendu Vaishnav, Massoud Pedram
    Alphabetic trees-theory and applications in layout-driven logicsynthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:58-69 [Journal]
  226. Hirendu Vaishnav, Massoud Pedram
    Delay-optimal clustering targeting low-power VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:799-812 [Journal]
  227. Qing Wu, Qinru Qiu, Massoud Pedram
    Estimation of peak power dissipation in VLSI circuits using thelimiting distributions of extreme order statistics. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:8, pp:942-956 [Journal]
  228. Diana Marculescu, Radu Marculescu, Massoud Pedram
    Stochastic sequential machine synthesis with application to constrained sequence generation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:658-681 [Journal]
  229. Massoud Pedram
    Power minimization in IC design: principles and applications. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1996, v:1, n:1, pp:3-56 [Journal]
  230. Massoud Pedram
    Introduction to special issue: Novel paradigms in system-level design. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:3, pp:535-536 [Journal]
  231. Afshin Abdollahi, Farzan Fallah, Massoud Pedram
    Leakage current reduction in CMOS VLSI circuits by input vector control. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:2, pp:140-154 [Journal]
  232. Peng Rong, Massoud Pedram
    An Analytical Model for Predicting the Remaining Battery Capacity of Lithium-Ion Batteries. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:441-451 [Journal]
  233. Ali Iranli, Wonbok Lee, Massoud Pedram
    HVS-Aware Dynamic Backlight Scaling in TFT-LCDs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:10, pp:1103-1116 [Journal]
  234. Behnam Amelifard, Massoud Pedram
    Optimal Selection of Voltage Regulator Modules in a Power Delivery Network. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:168-173 [Conf]
  235. Hwisung Jung, Massoud Pedram
    Dynamic power management under uncertain information. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1060-1065 [Conf]
  236. Shahin Nazarian, Massoud Pedram, Emre Tuncer, Tao Lin, Amir H. Ajami
    Modeling and Propagation of Noisy Waveforms in Static Timing Analysis [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  237. Ali Iranli, Hanif Fatemi, Massoud Pedram
    HEBS: Histogram Equalization for Backlight Scaling [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  238. Sung Kyu Lim, Massoud Pedram
    Introduction to special issue on demonstrable software systems and hardware platforms. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal]
  239. Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Chandramouli V. Kashyap
    Fast Interconnect and Gate Timing Analysis for Performance Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1383-1388 [Journal]
  240. Afshin Abdollahi, Farzan Fallah, Massoud Pedram
    A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:80-89 [Journal]
  241. Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
    Power estimation methods for sequential logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:404-416 [Journal]
  242. Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
    Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:4, pp:495- [Journal]
  243. Jui-Ming Chang, Massoud Pedram
    Energy minimization using multiple supply voltages. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:4, pp:436-443 [Journal]
  244. Qing Wu, Qinru Qiu, Massoud Pedram, Chih-Shun Ding
    Cycle-accurate macro-models for RT-level power analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:520-528 [Journal]
  245. Chih-Shun Ding, Cheng-Ta Hsieh, Massoud Pedram
    Improving the efficiency of Monte Carlo power estimation [VLSI]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:584-593 [Journal]
  246. Diana Marculescu, Radu Marculescu, Massoud Pedram
    Theoretical bounds for switching activity analysis in finite-state machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:3, pp:335-339 [Journal]
  247. Wei-Chung Cheng, Massoud Pedram
    Power-optimal encoding for a DRAM address bus. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:109-118 [Journal]
  248. Massoud Pedram, Qing Wu
    Battery-powered digital CMOS design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:601-607 [Journal]
  249. Payam Heydari, Massoud Pedram
    Ground bounce in digital VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:180-193 [Journal]
  250. Kihwan Choi, Kwanho Kim, Massoud Pedram
    Energy-Aware MPEG-4 FGS Streaming. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:1, pp:44-51 [Journal]
  251. Chang Woo Kang, Massoud Pedram
    A Leakage-aware Low Power Technology Mapping Algorithm Considering the Hot-Carrier Effect. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:2, pp:133-144 [Journal]
  252. Kihwan Choi, Wei-Chung Cheng, Massoud Pedram
    Frame-Based Dynamic Voltage and Frequency Scaling for an MPEG Player. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:1, pp:27-43 [Journal]

  253. Flow-Through-Queue based Power Management for Gigabit Ethernet Controller. [Citation Graph (, )][DBLP]


  254. A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms. [Citation Graph (, )][DBLP]


  255. A stochastic local hot spot alerting technique. [Citation Graph (, )][DBLP]


  256. Stochastic modeling of a thermally-managed multi-core system. [Citation Graph (, )][DBLP]


  257. A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack Effect. [Citation Graph (, )][DBLP]


  258. Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting. [Citation Graph (, )][DBLP]


  259. Resilient Dynamic Power Management under Uncertainty. [Citation Graph (, )][DBLP]


  260. Efficient compression and handling of current source model library waveforms. [Citation Graph (, )][DBLP]


  261. Optimizing the power delivery network in dynamically voltage scaled systems with uncertain power mode transition times. [Citation Graph (, )][DBLP]


  262. Efficient representation, stratification, and compression of variational CSM library waveforms using Robust Principle Component Analysis. [Citation Graph (, )][DBLP]


  263. Temperature-aware dynamic resource provisioning in a power-optimized datacenter. [Citation Graph (, )][DBLP]


  264. An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models. [Citation Graph (, )][DBLP]


  265. Statistical timing analysis of flip-flops considering codependent setup and hold times. [Citation Graph (, )][DBLP]


  266. In-order pulsed charge recycling in off-chip data buses. [Citation Graph (, )][DBLP]


  267. NBTI-aware flip-flop characterization and design. [Citation Graph (, )][DBLP]


  268. Green computing: reducing energy cost and carbon footprint of information processing systems. [Citation Graph (, )][DBLP]


  269. Sizing and placement of charge recycling transistors in MTCMOS circuits. [Citation Graph (, )][DBLP]


  270. Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing. [Citation Graph (, )][DBLP]


  271. Stochastic Dynamic Thermal Management: A Markovian Decision-based Approach. [Citation Graph (, )][DBLP]


  272. Probabilistic error propagation in logic circuits using the Boolean difference calculus. [Citation Graph (, )][DBLP]


  273. Characterization and design of sequential circuit elements to combat soft error. [Citation Graph (, )][DBLP]


  274. Power optimal MTCMOS repeater insertion for global buses. [Citation Graph (, )][DBLP]


  275. Design of an efficient power delivery network in an soc to enable dynamic power management. [Citation Graph (, )][DBLP]


  276. Minimizing power dissipation during write operation to register files. [Citation Graph (, )][DBLP]


  277. A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops. [Citation Graph (, )][DBLP]


  278. Minimizing data center cooling and server power costs. [Citation Graph (, )][DBLP]


  279. Maximum power transfer tracking for a photovoltaic-supercapacitor energy system. [Citation Graph (, )][DBLP]


  280. Hybrid electrical energy storage systems. [Citation Graph (, )][DBLP]


  281. Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors. [Citation Graph (, )][DBLP]


  282. Improving the Efficiency of Power Management Techniques by Using Bayesian Classification. [Citation Graph (, )][DBLP]


  283. Design and application of multimodal power gating structures. [Citation Graph (, )][DBLP]


  284. Minimizing the power consumption of a Chip Multiprocessor under an average throughput constraint. [Citation Graph (, )][DBLP]


  285. Multi-corner, energy-delay optimized, NBTI-aware flip-flop design. [Citation Graph (, )][DBLP]


  286. Continuous Frequency Adjustment Technique Based on Dynamic Workload Prediction. [Citation Graph (, )][DBLP]


  287. Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips. [Citation Graph (, )][DBLP]


  288. High-Level Modeling Approach for Analyzing the Effects of Traffic Models on Power and Throughput in Mesh-Based NoCs. [Citation Graph (, )][DBLP]


  289. Heterogeneous modulation for trading-off energy balancing with bandwidth efficiency in hierarchical sensor networks. [Citation Graph (, )][DBLP]


  290. Architectures for Silicon Nanoelectronics and Beyond. [Citation Graph (, )][DBLP]


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