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Sungjoo Yoo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Aimen Bouchhima, Sungjoo Yoo, Ahmed Amine Jerraya
    Fast and accurate timed execution of high level embedded software using HW/SW interface simulation model. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:469-474 [Conf]
  2. Youngchul Cho, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya
    Scheduler implementation in MP SoC design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:151-156 [Conf]
  3. Patrice Gerin, Sungjoo Yoo, Gabriela Nicolescu, Ahmed Amine Jerraya
    Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:63-68 [Conf]
  4. Byungil Jeong, Sungjoo Yoo, Sunghyun Lee, Kiyoung Choi
    Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:169-174 [Conf]
  5. Ikhwan Lee, Hyunsuk Kim, Peng Yang, Sungjoo Yoo, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo
    PowerViP: Soc power estimation framework at transaction level. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:551-558 [Conf]
  6. Gabriela Nicolescu, S. Martinez, Lobna Kriaa, Wassim Youssef, Sungjoo Yoo, Benoît Charlot, Ahmed Amine Jerraya
    Application of Multi-domain and Multi-language Cosimulation To an Optical MEM Switch Design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:426-434 [Conf]
  7. Sunghyun Lee, Sungjoo Yoo, Kiyoung Choi
    Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:199-204 [Conf]
  8. Sungjoo Yoo, Kiyoung Choi
    Optimistic distributed timed cosimulation based on thread simulation model. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:71-75 [Conf]
  9. Sungjoo Yoo, Kiyoung Choi
    Optimizing geographically distributed timed cosimulation by hierarchically grouped messages. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:100-104 [Conf]
  10. Sungjoo Yoo, Gabriela Nicolescu, Damien Lyonnard, Amer Baghdadi, Ahmed Amine Jerraya
    A generic wrapper architecture for multi-processor SoC cosimulation and design. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:195-200 [Conf]
  11. Sungjoo Yoo, Kyoungseok Rha, Youngchul Cho, Jinyong Jung, Kiyoung Choi
    Performance estimation of multiple-cache IP-based systems: case study of an interdependency problem and application of an extended shared memory model. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:77-81 [Conf]
  12. Sungpack Hong, Sungjoo Yoo, Sheayun Lee, Sangwoo Lee, Hye Jeong Nam, Bum-Seok Yoo, Jaehyung Hwang, Donghyun Song, Janghwan Kim, Jeongeun Kim, HoonSang Jin, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo
    Creation and utilization of a virtual platform for embedded software optimization: : an industrial case study. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:235-240 [Conf]
  13. Wander O. Cesário, Amer Baghdadi, Lovic Gauthier, Damien Lyonnard, Gabriela Nicolescu, Yanick Paviot, Sungjoo Yoo, Ahmed Amine Jerraya, Mario Diaz-Nava
    Component-based design approach for multicore SoCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:789-794 [Conf]
  14. Damien Lyonnard, Sungjoo Yoo, Amer Baghdadi, Ahmed Amine Jerraya
    Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:518-523 [Conf]
  15. Mohamed-Wassim Youssef, Sungjoo Yoo, Arif Sasongko, Yanick Paviot, Ahmed Amine Jerraya
    Debugging HW/SW interface for MPSoC: video encoder system design case study. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:908-913 [Conf]
  16. Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh
    Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:20132-20137 [Conf]
  17. Lovic Gauthier, Sungjoo Yoo, Ahmed Amine Jerraya
    Automatic generation and targeting of application specific operating systems and embedded systems software. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:679-685 [Conf]
  18. Jinyong Jung, Sungjoo Yoo, Kiyoung Choi
    Performance improvement of multi-processor systems cosimulation based on SW analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:749-753 [Conf]
  19. Gabriela Nicolescu, Sungjoo Yoo, Ahmed Amine Jerraya
    Mixed-level cosimulation for fine gradual refinement of communication in SoC design. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:754-759 [Conf]
  20. Sungjoo Yoo, Iuliana Bacivarov, Aimen Bouchhima, Yanick Paviot, Ahmed Amine Jerraya
    Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10550-10555 [Conf]
  21. Sungjoo Yoo, Ahmed Amine Jerraya
    Introduction to Hardware Abstraction Layers for SoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10336-10337 [Conf]
  22. Sungjoo Yoo, Jong-eun Lee, Jinyong Jung, Kyungseok Rha, Youngchul Cho, Kiyoung Choi
    Fast Hardware-Software Coverification by Optimistic Execution of Real Processor. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:663-668 [Conf]
  23. Sungjoo Yoo, Gabriela Nicolescu, Lovic Gauthier, Ahmed Amine Jerraya
    Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:620-627 [Conf]
  24. Sungjoo Yoo, Mohamed-Wassim Youssef, Aimen Bouchhima, Ahmed Amine Jerraya, Mario Diaz-Nava
    Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent Software. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1382-1383 [Conf]
  25. Byoungil Jeong, Sungjoo Yoo, Kiyoung Choi
    Exploiting Early Partial Reconfiguration of Run-Time Reconfigurable FPGAs in Embedded Systems Design. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:247- [Conf]
  26. Sungpack Hong, Sungjoo Yoo, HoonSang Jin, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo
    Runtime distribution-aware dynamic voltage scaling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:587-594 [Conf]
  27. Sunghyun Lee, Kiyoung Choi, Sungjoo Yoo
    An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:84-87 [Conf]
  28. Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima, Gabriela Nicolescu
    Validation in a Component-Based Design Flow for Multicore SoCs. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:162-167 [Conf]
  29. Gabriela Nicolescu, S. Martinez, Lobna Kriaa, Wassim Youssef, Sungjoo Yoo, Benoît Charlot, Ahmed Amine Jerraya
    Application of Multi-Domain and Multi-Language Cosimulation to an Optical MEM Switch Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:426-0 [Conf]
  30. Wander O. Cesário, Damien Lyonnard, Gabriela Nicolescu, Yanick Paviot, Sungjoo Yoo, Ahmed Amine Jerraya, Lovic Gauthier, Mario Diaz-Nava
    Multiprocessor SoC Platforms: A Component-Based Design Approach. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:6, pp:52-63 [Journal]
  31. Lovic Gauthier, Sungjoo Yoo, Ahmed Amine Jerraya
    Automatic generation and targeting of application-specificoperating systems and embedded systems software. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1293-1301 [Journal]
  32. Gabriela Nicolescu, Kjetil Svarstad, Wander O. Cesário, Lovic Gauthier, Damien Lyonnard, Sungjoo Yoo, P. Coste, Ahmed Amine Jerraya
    Desiderata pour la spécification et la conception des systèmes électroniques. [Citation Graph (0, 0)][DBLP]
    Technique et Science Informatiques, 2002, v:21, n:3, pp:291-314 [Journal]
  33. Sungjoo Yoo, Kiyoung Choi, Dong Sam Ha
    Performance improvement of geographically distributed cosimulation by hierarchically grouped messages. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:5, pp:492-502 [Journal]

  34. Communication Architecture Synthesis of Cascaded Bus Matrix. [Citation Graph (, )][DBLP]


  35. Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches. [Citation Graph (, )][DBLP]


  36. An industrial perspective of power-aware reliable SoC design. [Citation Graph (, )][DBLP]


  37. A practical approach of memory access parallelization to exploit multiple off-chip DDR memories. [Citation Graph (, )][DBLP]


  38. Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency. [Citation Graph (, )][DBLP]


  39. An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication. [Citation Graph (, )][DBLP]


  40. Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution. [Citation Graph (, )][DBLP]


  41. Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scaling. [Citation Graph (, )][DBLP]


  42. In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem. [Citation Graph (, )][DBLP]


  43. Event statistics and criticality-aware bitrate allocation to minimize energy consumption of memory-constrained wireless surveillance system. [Citation Graph (, )][DBLP]


  44. Entry control in network-on-chip for memory power reduction. [Citation Graph (, )][DBLP]


  45. Power Modeling of Solid State Disk for Dynamic Power Management Policy Design in Embedded Systems. [Citation Graph (, )][DBLP]


  46. A Network Congestion-Aware Memory Controller. [Citation Graph (, )][DBLP]


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