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Ahmed Amine Jerraya: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Aimen Bouchhima, Sungjoo Yoo, Ahmed Amine Jerraya
    Fast and accurate timed execution of high level embedded software using HW/SW interface simulation model. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:469-474 [Conf]
  2. Marius Bonaciu, Aimen Bouchhima, Mohamed-Wassim Youssef, Xi Chen, Wander O. Cesário, Ahmed Amine Jerraya
    High-level architecture exploration for MPEG4 encoder with custom parameters. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:372-377 [Conf]
  3. Aimen Bouchhima, Iuliana Bacivarov, Wassim Youssef, Marius Bonaciu, Ahmed Amine Jerraya
    Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:969-972 [Conf]
  4. Youngchul Cho, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya
    Scheduler implementation in MP SoC design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:151-156 [Conf]
  5. Rolf Ernst, Ahmed Amine Jerraya
    embedded system design with multiple languages: embedded tutorial. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:391-396 [Conf]
  6. Patrice Gerin, Sungjoo Yoo, Gabriela Nicolescu, Ahmed Amine Jerraya
    Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:63-68 [Conf]
  7. Sang-Il Han, Soo-Ik Chae, Ahmed Amine Jerraya
    Functional modeling techniques for efficient SW code generation of video codec applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:935-940 [Conf]
  8. Ahmed Amine Jerraya
    EuroSoC: towards a joint university/industry research infrastructure for system on chip and system in package. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:18- [Conf]
  9. Gabriela Nicolescu, S. Martinez, Lobna Kriaa, Wassim Youssef, Sungjoo Yoo, Benoît Charlot, Ahmed Amine Jerraya
    Application of Multi-domain and Multi-language Cosimulation To an Optical MEM Switch Design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:426-434 [Conf]
  10. Kjetil Svarstad, Nezih Ben-Fredj, Gabriela Nicolescu, Ahmed Amine Jerraya
    A higher level system communication model for object-oriented specification and design of embedded systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:69-77 [Conf]
  11. Nacer-Eddine Zergainoh, Katalin Popovici, Ahmed Amine Jerraya, Pascal Urard
    IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:612-618 [Conf]
  12. Ahmed Amine Jerraya, Kevin O'Brien, Tarek Ben Ismail
    Linking System Design Tools and Hardware Design Tools. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:345-351 [Conf]
  13. P. Coste, F. Hessel, P. LeMarrec, Zoltan Sugar, M. Romdhani, Rodolph Suescun, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya
    Multilanguage design of heterogeneous systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:54-58 [Conf]
  14. Jean-Marc Daveau, Gilberto Fernandes Marchioro, Ahmed Amine Jerraya
    Hardware/software co-design of an ATM network interface card: a case study. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:111-115 [Conf]
  15. Tarek Ben Ismail, Mohamed Abid, Ahmed Amine Jerraya
    COSMOS: a codesign approach for communicating systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1994, pp:17-24 [Conf]
  16. Adriano Sarmento, Lobna Kriaa, Arnaud Grasset, Mohamed-Wassim Youssef, Aimen Bouchhima, Frédéric Rousseau, Wander O. Cesário, Ahmed Amine Jerraya
    Service dependency graph: an efficient model for hardware/software interfaces modeling and generation for SoC design. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:261-266 [Conf]
  17. Markus Voss, Tarek Ben Ismail, Ahmed Amine Jerraya, Karl-Heinz Kapp
    Towards a theory for hardware/software codesign. [Citation Graph (0, 0)][DBLP]
    CODES, 1994, pp:173-180 [Conf]
  18. Sungjoo Yoo, Gabriela Nicolescu, Damien Lyonnard, Amer Baghdadi, Ahmed Amine Jerraya
    A generic wrapper architecture for multi-processor SoC cosimulation and design. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:195-200 [Conf]
  19. Pier Stanislao Paolucci, Ahmed Amine Jerraya, Rainer Leupers, Lothar Thiele, Piero Vicini
    SHAPES: : a tiled scalable software hardware architecture platform for embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:167-172 [Conf]
  20. E. Berrebi, Polen Kission, Serge Vernalde, S. De Troch, J. C. Herluison, J. Fréhel, Ahmed Amine Jerraya, Ivo Bolsens
    Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:573-578 [Conf]
  21. Wander O. Cesário, Amer Baghdadi, Lovic Gauthier, Damien Lyonnard, Gabriela Nicolescu, Yanick Paviot, Sungjoo Yoo, Ahmed Amine Jerraya, Mario Diaz-Nava
    Component-based design approach for multicore SoCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:789-794 [Conf]
  22. Ferid Gharsalli, Samy Meftali, Frédéric Rousseau, Ahmed Amine Jerraya
    Automatic generation of embedded memory wrapper for multiprocessor SoC. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:596-601 [Conf]
  23. Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik Chae, Ahmed Amine Jerraya
    An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:250-255 [Conf]
  24. Sang-Il Han, Xavier Guerin, Soo-Ik Chae, Ahmed Amine Jerraya
    Buffer memory optimization for video codec application modeled in Simulink. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:689-694 [Conf]
  25. Ahmed Amine Jerraya, Aimen Bouchhima, Frédéric Pétrot
    Programming models and HW-SW interfaces abstraction for multi-processor SoC. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:280-285 [Conf]
  26. Ahmed Amine Jerraya, P. Varinot, R. Jamier, Bernard Courtois
    Principles of the SYCO compiler. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:715-721 [Conf]
  27. Polen Kission, Hong Ding, Ahmed Amine Jerraya
    Structured Design Methodology for High-Level Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:466-471 [Conf]
  28. Clifford Liem, Marco Cornero, Miguel Santana, Pierre G. Paulin, Ahmed Amine Jerraya, Jean-Marc Gentit, Jean Lopez, Xavier Figari, Laurent Bergher
    Am Embedded System Case Study: The Firm Ware Development Environment for a Multimedia Audio Processor. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:780-785 [Conf]
  29. Clifford Liem, Pierre G. Paulin, Ahmed Amine Jerraya
    Address Calculation for Retargetable Compilation and Exploration of Instruction-Set Architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:597-600 [Conf]
  30. Damien Lyonnard, Sungjoo Yoo, Amer Baghdadi, Ahmed Amine Jerraya
    Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:518-523 [Conf]
  31. Imed Moussa, Zoltan Sugar, Rodolph Suescun, Mario Diaz-Nava, Marco Pavesi, Salvatore Crudo, Luca Gazi, Ahmed Amine Jerraya
    Comparing RTL and Behavioral Design Methodologies in the Case of a 2M-Transistor ATM Shaper. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:598-603 [Conf]
  32. Mohamed-Wassim Youssef, Sungjoo Yoo, Arif Sasongko, Yanick Paviot, Ahmed Amine Jerraya
    Debugging HW/SW interface for MPSoC: video encoder system design case study. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:908-913 [Conf]
  33. Amer Baghdadi, Damien Lyonnard, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya
    An efficient architecture model for systematic design of application-specific multiprocessor SoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:55-63 [Conf]
  34. Joseph Borel, G. Matheron, Ahmed Amine Jerraya, S. Resve, M. Rogers, Wolfgang Rosenstiel, Irmtraud Rugen-Herzig, F. Theewen
    MEDEA+ and ITRS Roadmaps. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:328-329 [Conf]
  35. Florin Dumitrascu, Iuliana Bacivarov, Lorenzo Pieralisi, Marius Bonaciu, Ahmed Amine Jerraya
    Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:166-171 [Conf]
  36. Mohamed-Anouar Dziri, Wander O. Cesário, Flávio Rech Wagner, Ahmed Amine Jerraya
    Unified Component Integration Flow for Multi-Processor SoC Design and Validation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1132-1137 [Conf]
  37. Lovic Gauthier, Ahmed Amine Jerraya
    Cycle-True Simulation of the ST10 Microcontroller. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:742- [Conf]
  38. Lovic Gauthier, Sungjoo Yoo, Ahmed Amine Jerraya
    Automatic generation and targeting of application specific operating systems and embedded systems software. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:679-685 [Conf]
  39. A. Jemai, Polen Kission, Ahmed Amine Jerraya
    Architectural Simulation in the Context of Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:590-595 [Conf]
  40. Ahmed Amine Jerraya, Rolf Ernst
    Multi-Language System Design. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:696-0 [Conf]
  41. Ahmed Amine Jerraya, G. Matheron
    Electronic system design methodology: Europe's positioning. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:720-721 [Conf]
  42. Gabriela Nicolescu, Sungjoo Yoo, Ahmed Amine Jerraya
    Mixed-level cosimulation for fine gradual refinement of communication in SoC design. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:754-759 [Conf]
  43. Kjetil Svarstad, Gabriela Nicolescu, Ahmed Amine Jerraya
    A model for describing communication between aggregate objects in the specification and design of embedded systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:77-85 [Conf]
  44. Sungjoo Yoo, Iuliana Bacivarov, Aimen Bouchhima, Yanick Paviot, Ahmed Amine Jerraya
    Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10550-10555 [Conf]
  45. Sungjoo Yoo, Ahmed Amine Jerraya
    Introduction to Hardware Abstraction Layers for SoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10336-10337 [Conf]
  46. Sungjoo Yoo, Gabriela Nicolescu, Lovic Gauthier, Ahmed Amine Jerraya
    Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:620-627 [Conf]
  47. Sungjoo Yoo, Mohamed-Wassim Youssef, Aimen Bouchhima, Ahmed Amine Jerraya, Mario Diaz-Nava
    Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent Software. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1382-1383 [Conf]
  48. Ahmed Amine Jerraya
    Long Term Trends for Embedded System Design. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:20-26 [Conf]
  49. Aimen Bouchhima, Xi Chen, Frédéric Pétrot, Wander O. Cesário, Ahmed Amine Jerraya
    A unified HW/SW interface model to remove discontinuities between HW and SW design. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2005, pp:159-163 [Conf]
  50. Tarek Ben Ismail, Kevin O'Brien, Ahmed Amine Jerraya
    Interactive System-level Partitioning with PARTIF. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:464-468 [Conf]
  51. Salvador Mir, Benoît Charlot, Gabriela Nicolescu, P. Coste, Fabien Parrain, Nacer-Eddine Zergainoh, Bernard Courtois, Ahmed Amine Jerraya, Márta Rencz
    Towards design and validation of mixed-technology SOCs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:29-33 [Conf]
  52. Gilberto Fernandes Marchioro, Jean-Marc Daveau, Ahmed Amine Jerraya
    Transformational partitioning for co-design of multiprocessor systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:508-515 [Conf]
  53. Wander O. Cesário, Ahmed Amine Jerraya, Zoltan Sugar, Imed Moussa
    Rethinking Behavioral Synthesis for a Better Integration within Existing Design Flows. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:513-518 [Conf]
  54. F. Hessel, P. Coste, Gabriela Nicolescu, P. LeMarrec, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya
    Multi-Level Communication Synthesis of Heterogeneous Multilanguage Specification. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:525-0 [Conf]
  55. I. Park, Kevin O'Brien, Ahmed Amine Jerraya
    AMICAL: Architectural Synthesis based on VHDL. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:219-234 [Conf]
  56. F. Hessel, P. LeMarrec, Carlos A. Valderrama, M. Romdhani, Ahmed Amine Jerraya
    MCI- Multilanguage Distributed Co- Simulation Tool. [Citation Graph (0, 0)][DBLP]
    DIPES, 1998, pp:191-202 [Conf]
  57. Amer Baghdadi, Nacer-Eddine Zergainoh, Damien Lyonnard, Ahmed Amine Jerraya
    Generic Architecture Platform for Multiprocessor System-On-Chip Design. [Citation Graph (0, 0)][DBLP]
    DIPES, 2000, pp:53-64 [Conf]
  58. Nacer-Eddine Zergainoh, Amer Baghdadi, Ludovic Tambour, Damien Lyonnard, Lovic Gauthier, Ahmed Amine Jerraya
    Framework for System Design, Validation and Fast Prototyping of Multiprocessor System-On-Chip. [Citation Graph (0, 0)][DBLP]
    DIPES, 2000, pp:99-110 [Conf]
  59. Samy Meftali, Ferid Gharsalli, Frédéric Rousseau, Ahmed Amine Jerraya
    Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared Memory. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:193-204 [Conf]
  60. Ahmed Amine Jerraya, Damien Lyonnard, Samy Meftali, Frédéric Rousseau, Ferid Gharsalli
    Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:26-31 [Conf]
  61. Ahmed Amine Jerraya, Pierre G. Paulin, Richard Norman, Feliks J. Welfeld
    Programming models for network processors (Panel). [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:202- [Conf]
  62. Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima, Gabriela Nicolescu
    Validation in a Component-Based Design Flow for Multicore SoCs. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:162-167 [Conf]
  63. Wander O. Cesário, Zoltan Sugar, Imed Moussa, Ahmed Amine Jerraya
    Efficient Integration of Behavioral Synthesis with Existing Design Flows. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:85-90 [Conf]
  64. Samy Meftali, Ferid Gharsalli, Frédéric Rousseau, Ahmed Amine Jerraya
    An optimal memory allocation for application-specific multiprocessor system-on-chip. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:19-24 [Conf]
  65. Clifford Liem, Pierre G. Paulin, Marco Cornero, Ahmed Amine Jerraya
    Industrial experience using rule-driven retargetable code generation for multimedia applications. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:60-68 [Conf]
  66. Jean-Marc Daveau, Tarek Ben Ismail, Ahmed Amine Jerraya
    Synthesis of system-level communication by an allocation-based approach. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:150-155 [Conf]
  67. F. Hunsinger, Sebastien Francois, Ahmed Amine Jerraya
    Definition of a systematic method for the generation of software test programs allowing the functional verification of System On Chip (SoC). [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:11-0 [Conf]
  68. F. Hessel, P. Coste, P. LeMarrec, Nacer-Eddine Zergainoh, Jean-Marc Daveau, Ahmed Amine Jerraya
    Communication Interface Synthesis for Multilanguage Specifications. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 1999, pp:15-20 [Conf]
  69. Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, T. Roudier, Ahmed Amine Jerraya
    Design Space Exploration for Hardware/Software Codesign of Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:8-13 [Conf]
  70. Lovic Gauthier, Ahmed Amine Jerraya
    Cycle-True Simulation of the ST10 Microcontroller Including the Core and the Peripherals. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:60-65 [Conf]
  71. Ferid Gharsalli, Amer Baghdadi, Marius Bonaciu, Giedrius Majauskas, Wander O. Cesário, Ahmed Amine Jerraya
    An Efficient Architecture for the Implementation of Message Passing Programming Model on Massive Multiprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2004, pp:80-87 [Conf]
  72. Arnaud Grasset, Frédéric Rousseau, Ahmed Amine Jerraya
    Network Interface Generation for MPSOC: From Communication Service Requirements to RTL Implementation. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2004, pp:66-69 [Conf]
  73. Arnaud Grasset, Frédéric Rousseau, Ahmed Amine Jerraya
    Automatic Generation of Component Wrappers by Composition of Hardware Library Elements Starting from Communication Service Specification. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:47-53 [Conf]
  74. Wander O. Cesário, Gabriela Nicolescu, Lovic Gauthier, Damien Lyonnard, Ahmed Amine Jerraya
    Colif: a Multilevel Design Representation for Application-Specific Multiprocessor System-on-Chip Design. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2001, pp:110-115 [Conf]
  75. Lobna Kriaa, Aimen Bouchhima, Wassim Youssef, Frédéric Pétrot, Anne-Marie Fouillart, Ahmed Amine Jerraya
    Service Based Component Design Approach for Flexible Hardware/Software Interface Modeling. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2006, pp:156-162 [Conf]
  76. P. LeMarrec, Carlos A. Valderrama, F. Hessel, Ahmed Amine Jerraya, M. Attia, O. Cayrol
    Hardware, Software and Mechanical Cosimulation for Automotive Applications. [Citation Graph (0, 0)][DBLP]
    International Workshop on Rapid System Prototyping, 1998, pp:202-206 [Conf]
  77. R. Lemaire, Fabien Clermidy, Y. Durand, D. Lattard, Ahmed Amine Jerraya
    Performance Evaluation of a NoC-Based Design for MC-CDMA Telecommunications Using NS-2. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:24-30 [Conf]
  78. Adriano Sarmento, Wander O. Cesário, Ahmed Amine Jerraya
    Automatic Building of Executable Models from Abstract SoC Architectures Made of Heterogeneous Subsystems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2004, pp:88-95 [Conf]
  79. Arif Sasongko, Amer Baghdadi, Frédéric Rousseau, Ahmed Amine Jerraya
    Embedded Application Prototyping on a Communication-Restricted Reconfigurable. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2003, pp:33-39 [Conf]
  80. Benaoumeur Senouci, Aimen Bouchhima, Frédéric Rousseau, Frédéric Pétrot, Ahmed Amine Jerraya
    Fast Prototyping of POSIX Based Applications on a Multiprocessor SoC Architecture: "Hardware-Dependent Software Oriented Approach". [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2006, pp:69-75 [Conf]
  81. Ludovic Tambour, Nacer-Eddine Zergainoh, Pascal Urard, Henri Michel, Ahmed Amine Jerraya
    An Efficient Methodology and Semi-Automated Flow for Design and Validation of Complex Digital Signal Processing ASICS Macro-Cells. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2003, pp:56-63 [Conf]
  82. Ahmed Amine Jerraya, Pierre G. Paulin, Simon Curry
    Meta VHDL for Higher Level Controller Modeling and Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:215-224 [Conf]
  83. Gabriela Nicolescu, S. Martinez, Lobna Kriaa, Wassim Youssef, Sungjoo Yoo, Benoît Charlot, Ahmed Amine Jerraya
    Application of Multi-Domain and Multi-Language Cosimulation to an Optical MEM Switch Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:426-0 [Conf]
  84. Tarek Ben Ismail, Ahmed Amine Jerraya
    Synthesis Steps and Design Models for Codesign. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1995, v:28, n:2, pp:44-52 [Journal]
  85. Ahmed Amine Jerraya, Hannu Tenhunen, Wayne Wolf
    Guest Editors' Introduction: Multiprocessor Systems-on-Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2005, v:38, n:7, pp:36-40 [Journal]
  86. Ahmed Amine Jerraya, Wayne Wolf
    Hardware/Software Interface Codesign for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2005, v:38, n:2, pp:63-69 [Journal]
  87. Wander O. Cesário, Damien Lyonnard, Gabriela Nicolescu, Yanick Paviot, Sungjoo Yoo, Ahmed Amine Jerraya, Lovic Gauthier, Mario Diaz-Nava
    Multiprocessor SoC Platforms: A Component-Based Design Approach. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:6, pp:52-63 [Journal]
  88. Wander O. Cesário, Gabriela Nicolescu, Lovic Gauthier, Damien Lyonnard, Ahmed Amine Jerraya
    Colif: A Design Representation for Application-Specific Multiprocessor SOCs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:5, pp:8-20 [Journal]
  89. Ahmed Amine Jerraya
    Two Enduring Questions for Computer Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:3, pp:128-0 [Journal]
  90. Ahmed Amine Jerraya
    Hot Topics at HLDVT 02. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:92-0 [Journal]
  91. Clifford Liem, François Naçabal, Carlos A. Valderrama, Pierre G. Paulin, Ahmed Amine Jerraya
    System-on-a-Chip Cosimulation and Compilation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:2, pp:16-25 [Journal]
  92. Wayne Wolf, Ahmed Amine Jerraya
    Application-Specific System-on-a-Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:5, pp:7-0 [Journal]
  93. Flávio Rech Wagner, Wander O. Cesário, Luigi Carro, Ahmed Amine Jerraya
    Strategies for the integration of hardware and software IP components in embedded systems-on-chip. [Citation Graph (0, 0)][DBLP]
    Integration, 2004, v:37, n:4, pp:223-252 [Journal]
  94. Wander O. Cesário, Lovic Gauthier, Damien Lyonnard, Gabriela Nicolescu, Ahmed Amine Jerraya
    Object-based hardware/software component interconnection model for interface design in system-on-a-chip circuits. [Citation Graph (0, 0)][DBLP]
    Journal of Systems and Software, 2004, v:70, n:3, pp:229-244 [Journal]
  95. Maher K. Rahmouni, Kevin O'Brien, Ahmed Amine Jerraya
    A Loop-Based Scheduling Algorithm for Hardware Description Languages. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1994, v:4, n:, pp:351-364 [Journal]
  96. Lovic Gauthier, Sungjoo Yoo, Ahmed Amine Jerraya
    Automatic generation and targeting of application-specificoperating systems and embedded systems software. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1293-1301 [Journal]
  97. Ahmed Amine Jerraya, Trevor N. Mudge
    Guest editorial: Concurrent hardware and software design for multiprocessor SoC. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:2, pp:259-262 [Journal]
  98. Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, Ahmed Amine Jerraya
    Combining a Performance Estimation Methodology with a Hardware/Software Codesign Flow Supporting Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 2002, v:28, n:9, pp:822-831 [Journal]
  99. Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, Ahmed Amine Jerraya
    Exploration de l'espace des solutions architecturales dans le codesign. [Citation Graph (0, 0)][DBLP]
    Technique et Science Informatiques, 2002, v:21, n:1, pp:9-35 [Journal]
  100. Ferid Gharsalli, Frédéric Rousseau, Ahmed Amine Jerraya
    Conception des interfaces logiciel-matériel pour l'intégration des mémoires globales dans les systèmes monopuces. [Citation Graph (0, 0)][DBLP]
    Technique et Science Informatiques, 2005, v:24, n:4, pp:369-394 [Journal]
  101. Gabriela Nicolescu, Kjetil Svarstad, Wander O. Cesário, Lovic Gauthier, Damien Lyonnard, Sungjoo Yoo, P. Coste, Ahmed Amine Jerraya
    Desiderata pour la spécification et la conception des systèmes électroniques. [Citation Graph (0, 0)][DBLP]
    Technique et Science Informatiques, 2002, v:21, n:3, pp:291-314 [Journal]
  102. Nacer-Eddine Zergainoh, Ludovic Tambour, Ahmed Amine Jerraya
    Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:349-360 [Journal]
  103. Xavier Guerin, Katalin Popovici, Wassim Youssef, Frédéric Rousseau, Ahmed Amine Jerraya
    Flexible Application Software Generation for Heterogeneous Multi-Processor System-on-Chip. [Citation Graph (0, 0)][DBLP]
    COMPSAC (1), 2007, pp:279-286 [Conf]
  104. Kai Huang, Sang-Il Han, Katalin Popovici, Lisane B. de Brisolara, Xavier Guerin, Lei Li, Xiaolang Yan, Soo-Ik Chae, Luigi Carro, Ahmed Amine Jerraya
    Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:39-42 [Conf]
  105. Ahmed Amine Jerraya
    HW/SW implementation from abstract architecture models. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1470-1471 [Conf]
  106. Youngchul Cho, Nacer-Eddine Zergainoh, Kiyoung Choi, Ahmed Amine Jerraya
    Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:195-201 [Conf]
  107. Katalin Popovici, Xavier Guerin, Frédéric Rousseau, Pier Stanislao Paolucci, Ahmed Amine Jerraya
    Efficient Software Development Platforms for Multimedia Applications at Different Abstraction Levels. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:113-122 [Conf]
  108. Youngchul Cho, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya, Kiyoung Choi
    Buffer Size Reduction through Control-Flow Decomposition. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2007, pp:183-190 [Conf]
  109. Flávio Rech Wagner, Wander O. Cesário, Ahmed Amine Jerraya
    Hardware/software IP integration using the ROSES design environment. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2007, v:6, n:3, pp:- [Journal]
  110. Jean-Marc Daveau, Gilberto Fernandes Marchioro, Tarek Ben Ismail, Ahmed Amine Jerraya
    Protocol selection and interface generation for HW-SW codesign. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:136-144 [Journal]
  111. Ahmed Amine Jerraya, Gert Goossens
    Guest Editorial Introduction to the Special Issue on the Eighth IEEE International Symposium on System Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:57-58 [Journal]

  112. Flexible and Executable Hardware/Software Interface Modeling for Multiprocessor SoC Design Using SystemC. [Citation Graph (, )][DBLP]


  113. Software Performance Estimation in MPSoC Design. [Citation Graph (, )][DBLP]


  114. Flexible and abstract communication and interconnect modeling for MPSoC. [Citation Graph (, )][DBLP]


  115. Automatically Realising Embedded Systems from High-Level Functional Models. [Citation Graph (, )][DBLP]


  116. ReCode: the design and re-design of the instruction codes for embedded instruction-set processors. [Citation Graph (, )][DBLP]


  117. Panel session - Multicore, will Startups drive innovation? [Citation Graph (, )][DBLP]


  118. Embedded tutorial - Understanding multicore technologies. [Citation Graph (, )][DBLP]


  119. Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem. [Citation Graph (, )][DBLP]


  120. VHDL based design methodology for hierarchy and component re-use. [Citation Graph (, )][DBLP]


  121. Composing ActivityCharts/StateCharts, SDL and SAO specifications for codesign in avionics. [Citation Graph (, )][DBLP]


  122. Formulation and evaluation of scheduling techniques for control flow graphs. [Citation Graph (, )][DBLP]


  123. NAUTILE: a safe environment for silicon compilation. [Citation Graph (, )][DBLP]


  124. Integrating Abstract NoC Models within MPSoC Design. [Citation Graph (, )][DBLP]


  125. Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC. [Citation Graph (, )][DBLP]


  126. Simulink based hardware-software codesign flow for heterogeneous MPSoC. [Citation Graph (, )][DBLP]


  127. Prototyping Multiprocessor System-on-Chip Applications: A Platform-Based Approach. [Citation Graph (, )][DBLP]


  128. Roundtable: Envisioning the Future for Multiprocessor SoC. [Citation Graph (, )][DBLP]


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