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C.-J. Richard Shi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Youcef Bourai, C.-J. Richard Shi
    Symmetry Detection for Automatic Analog-Layout Recycling. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:5-8 [Conf]
  2. Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi
    Hierarchical extraction and verification of symmetry constraints for analog layout automation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:400-405 [Conf]
  3. Zhao Li, C.-J. Richard Shi
    A quasi-newton preconditioned Newton-Krylov method for robust and efficient time-domain simulation of integrated circuits with strong parasitic couplings. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:402-407 [Conf]
  4. Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, C.-J. Richard Shi
    Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:394-399 [Conf]
  5. Zhao Li, Ravikanth Suravarapu, Roy Hartono, Sambuddha Bhattacharya, Kartikeya Mayaram, C.-J. Richard Shi
    CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:163-168 [Conf]
  6. Tao Pi, C.-J. Richard Shi
    Analog-testability analysis by determinant-decision-diagrams based symbolic analysis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:541-546 [Conf]
  7. C.-J. Richard Shi
    Mixed-Signal Hardware Description Languages in the Era of System-on-Silicon: Challenges and Opportunities (Abstract of Embedded Tutorial). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:543- [Conf]
  8. C.-J. Shi, Janusz A. Brzozowski
    A framework for the analysis and design of algorithms for a class of VLSI-CAD optimization problems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  9. Guoyong Shi, C.-J. Richard Shi
    Parametric reduced order modeling for interconnect analysis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:774-779 [Conf]
  10. C.-J. Richard Shi, Michael W. Tian
    Automatic Test Generation for Linear Analog Circuits under Parameter Variations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:501-506 [Conf]
  11. Xiang-Dong Tan, C.-J. Richard Shi
    Symbolic circuit-noise analysis and modeling with determinant decision diagrams. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:283-288 [Conf]
  12. Xiang-Dong Tan, C.-J. Richard Shi
    Balanced Multi-Level Multi-Way Partitioning of Large Analog Circuits for Hierarchical Symbolic Analysis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:1-4 [Conf]
  13. Lei Yang, Manyuan Shen, Hui Liu, C.-J. Richard Shi
    An FPGA implementation of low-density parity-check code decoder with multi-rate capability. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:760-763 [Conf]
  14. Lili Zhou, Cherry Wakayama, Nuttorn Jangkrajarng, Bo Hu, C.-J. Richard Shi
    A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:92-93 [Conf]
  15. Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi
    Correct-by-construction layout-centric retargeting of large analog designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:139-144 [Conf]
  16. Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi
    Template-driven parasitic-aware optimization of analog integrated circuit layouts. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:644-647 [Conf]
  17. Alicia Manthe, Zhao Li, C.-J. Richard Shi
    Symbolic analysis of analog circuits with hard nonlinearity. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:542-545 [Conf]
  18. Tao Pi, C.-J. Richard Shi
    Multi-terminal determinant decision diagrams: a new approach to semi-symbolic analysis of analog integrated circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:19-22 [Conf]
  19. Sheldon X.-D. Tan, C.-J. Richard Shi
    Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:550-554 [Conf]
  20. Xiang-Dong Tan, C.-J. Richard Shi, Dragos Lungeanu, Jyh-Chwen Lee, Li-Pen Yuan
    Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear Programmings. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:78-83 [Conf]
  21. Michael W. Tian, C.-J. Richard Shi
    Rapid Frequency-Domain Analog Fault Simulation Under Parameter Tolerances. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:275-280 [Conf]
  22. Zhao Li, C.-J. Richard Shi
    An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:752-757 [Conf]
  23. Youcef Bourai, C.-J. Richard Shi
    Layout Compaction for Yield Optimization via Critical Area Minimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:122-0 [Conf]
  24. Dragos Lungeanu, C.-J. Richard Shi
    Parallel and Distributed VHDL Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:658-662 [Conf]
  25. Alicia Manthe, Zhao Li, C.-J. Richard Shi, Kartikeya Mayaram
    Symbolic Analysis of Nonlinear Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11108-11109 [Conf]
  26. Xiang-Dong Tan, C.-J. Richard Shi
    Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits using Determinant Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:448-453 [Conf]
  27. Michael W. Tian, C.-J. Richard Shi
    Efficient DC Fault Simulation of Nonlinear Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:899-904 [Conf]
  28. Bo Wan, C.-J. Richard Shi
    Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1310-1315 [Conf]
  29. Lei Yang, Cherry Wakayama, C.-J. Richard Shi
    Noise aware behavioral modeling of the E-Delta fractional-N frequency synthesizer. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:138-142 [Conf]
  30. Bo Hu, C.-J. Richard Shi
    Fast-yet-accurate PVT simulation by combined direct and iterative methods. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:495-501 [Conf]
  31. Zhao Li, C.-J. Richard Shi
    SILCA: Fast-Yet-Accurate Time-Domain Simulation of VLSI Circuits with Strong Parasitic Coupling Effects. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:793-800 [Conf]
  32. Dragos Lungeanu, C.-J. Richard Shi
    Distributed simulation of VLSI systems via lookahead-free self-adaptive optimistic and conservative synchronization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:500-504 [Conf]
  33. C.-J. Richard Shi, Xiang-Dong Tan
    Symbolic analysis of large analog circuits with determinant decision diagrams. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:366-373 [Conf]
  34. Lei Yang, C.-J. Richard Shi
    FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:741-747 [Conf]
  35. Nuttorn Jangkrajarng, Lihong Zhang, Sambuddha Bhattacharya, Nathan Kohagen, C.-J. Richard Shi
    Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:342-348 [Conf]
  36. Olivier Coudert, C.-J. Richard Shi
    Exact Dichotomy-based Constrained Encodi. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:426-431 [Conf]
  37. Dragos Lungeanu, C.-J. Richard Shi
    Distributed Event-Driven Simulation of VHDL-SPICE Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:302-307 [Conf]
  38. Alicia Manthe, C.-J. Richard Shi
    Lower Bound Based DDD Minimization for Efficient Symbolic Circuit Analysis. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:374-379 [Conf]
  39. Sambuddha Bhattacharya, C.-J. Richard Shi
    Concurrent logic and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:660-663 [Conf]
  40. Bo Hu, Zhao Li, Lili Zhou, C.-J. Richard Shi, Kwang-Hyun Baek, Myung-Jun Choe
    Model-compiler based efficient statistical circuit analysis: an industry case study of a 4 GHz/6-bit ADC/DAC/DEMUX ASIC. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5621-5624 [Conf]
  41. Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, C.-J. Richard Shi
    Automatic analog layout retargeting for new processes and device sizes. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:704-707 [Conf]
  42. Zhao Li, C.-J. Richard Shi
    A coupled iterative/direct method for efficient time-domain simulation of nonlinear circuits with power/ground networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:165-168 [Conf]
  43. Vikram Jandhyala, Yong Wang, Dipanjan Gope, C.-J. Richard Shi
    Coupled Electromagnetic-Circuit Simulation of Arbitrarily-Shaped Conducting Structures Using Triangular Meshes. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:38-42 [Conf]
  44. Pavel V. Nikitin, Vikram Jandhyala, Daniel White, Nathan Champagne, John D. Rockway, C.-J. Richard Shi, Chuanyi Yang, Yong Wang, Gong Ouyang, Rob Sharpe, John W. Rockway
    Modeling and Simulation of Circuit-Electromagnetic Effects in Electronic Design Flow. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:244-249 [Conf]
  45. Vikram Jandhyala, Yasuo Kuga, David J. Allstot, C.-J. Richard Shi
    Bridging Circuits and Electromagnetics in a Curriculum Aimed at Microelectronic Analog and Microwave Simulation and Design. [Citation Graph (0, 0)][DBLP]
    MSE, 2005, pp:45-46 [Conf]
  46. Pavel V. Nikitin, Winnie Yam, C.-J. Richard Shi
    Parametric Equivalent Circuit Extraction for VLSI Structures. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:198-203 [Conf]
  47. Roy Hartono, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, C.-J. Richard Shi
    Automatic Device Layout Generation for Analog Layout Retargeting. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:457-462 [Conf]
  48. N. J. Godambe, C.-J. Richard Shi
    Behavioral level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMS. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:177-183 [Conf]
  49. Michael W. Tian, C.-J. Richard Shi
    Nonlinear Analog DC Fault Simulation by One-Step Relaxation. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:126-131 [Conf]
  50. C.-J. Richard Shi, Janusz A. Brzozowski
    A Characterization of Signed Hypergraphs and Its Applications to VLSI Via Minimization and Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    Discrete Applied Mathematics, 1999, v:90, n:1-3, pp:223-243 [Journal]
  51. C.-J. Richard Shi, Anthony Vannelli, Jiri Vlach
    Performance-Driven Layer Assignment by Integer Linear Programming and Path-Constrained Hypergraph Partitioning. [Citation Graph (0, 0)][DBLP]
    J. Heuristics, 1997, v:3, n:3, pp:225-243 [Journal]
  52. Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, C.-J. Richard Shi
    IPRAIL - intellectual property reuse-based analog IC layout automation. [Citation Graph (0, 0)][DBLP]
    Integration, 2003, v:36, n:4, pp:237-262 [Journal]
  53. Sheldon X.-D. Tan, C.-J. Richard Shi
    Balanced multi-level multi-way partitioning of analog integrated circuits for hierarchical symbolic analysis. [Citation Graph (0, 0)][DBLP]
    Integration, 2003, v:34, n:1-2, pp:65-86 [Journal]
  54. Lei Yang, C.-J. Richard Shi
    FROSTY: A program for fast extraction of high-level structural representation from circuit description for industrial CMOS circuits. [Citation Graph (0, 0)][DBLP]
    Integration, 2006, v:39, n:4, pp:311-339 [Journal]
  55. C.-J. Richard Shi
    Entity Overloading for Mixed-Signal Abstraction in VHDL. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:3, pp:633-644 [Journal]
  56. Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi
    Multilevel symmetry-constraint generation for retargeting large analog layouts. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:945-960 [Journal]
  57. Zhao Li, C.-J. Richard Shi
    SILCA: SPICE-accurate iterative linear-centric analysis for efficient time-domain Simulation of VLSI circuits with strong parasitic couplings. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1087-1103 [Journal]
  58. Guoyong Shi, Bo Hu, C.-J. Richard Shi
    On symbolic model order reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1257-1272 [Journal]
  59. C.-J. Richard Shi, Sheldon X.-D. Tan
    Canonical symbolic analysis of large analog circuits withdeterminant decision diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:1-18 [Journal]
  60. C.-J. Richard Shi, Sheldon X.-D. Tan
    Compact representation and efficient generation of s-expandedsymbolic network functions for computer-aided analog circuit design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:7, pp:813-827 [Journal]
  61. C.-J. Richard Shi, Michael W. Tian, Guoyong Shi
    Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1392-1400 [Journal]
  62. Sheldon X.-D. Tan, C.-J. Richard Shi
    Hierarchical symbolic analysis of analog integrated circuits viadeterminant decision diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:4, pp:401-412 [Journal]
  63. Sheldon X.-D. Tan, C.-J. Richard Shi
    Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:277-284 [Journal]
  64. Sheldon X.-D. Tan, C.-J. Richard Shi
    Efficient approximation of symbolic expressions for analog behavioral modeling and analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:907-918 [Journal]
  65. Sheldon X.-D. Tan, C.-J. Richard Shi, Jyh-Chwen Lee
    Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:12, pp:1678-1684 [Journal]
  66. Jiri Vlach, James A. Barby, Anthony Vannelli, T. Talkhan, C.-J. Richard Shi
    Group delay as an estimate of delay in logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:7, pp:949-953 [Journal]
  67. C.-J. Richard Shi, Janusz A. Brzozowski
    Cluster-cover a theoretical framework for a class of VLSI-CAD optimization problems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:1, pp:76-107 [Journal]
  68. C.-J. Richard Shi, Michael W. Tian
    Simulation and sensitivity of linear analog circuits under parameter variations by Robust interval analysis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1999, v:4, n:3, pp:280-312 [Journal]
  69. Bo Hu, C.-J. Richard Shi
    Improved automatic differentiation method for efficient model compiler. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  70. Pavel V. Nikitin, C.-J. Richard Shi
    VHDL-AMS based modeling and simulation of mixed-technology microsystems: a tutorial. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:3, pp:261-273 [Journal]

  71. A Graph Reduction Approach to Symbolic Circuit Analysis. [Citation Graph (, )][DBLP]


  72. Symmetry-aware placement with transitive closure graphs for analog layout design. [Citation Graph (, )][DBLP]


  73. Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining. [Citation Graph (, )][DBLP]


  74. Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits. [Citation Graph (, )][DBLP]


  75. A 6-11GHz multi-phase VCO design with active inductors. [Citation Graph (, )][DBLP]


  76. A quantum-dot light-harvesting architecture using deterministic phase control. [Citation Graph (, )][DBLP]


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