Zhao Li, C.-J. Richard Shi A quasi-newton preconditioned Newton-Krylov method for robust and efficient time-domain simulation of integrated circuits with strong parasitic couplings. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2006, pp:402-407 [Conf]
C.-J. Richard Shi Mixed-Signal Hardware Description Languages in the Era of System-on-Silicon: Challenges and Opportunities (Abstract of Embedded Tutorial). [Citation Graph (0, 0)][DBLP] ASP-DAC, 1998, pp:543- [Conf]
Tao Pi, C.-J. Richard Shi Multi-terminal determinant decision diagrams: a new approach to semi-symbolic analysis of analog integrated circuits. [Citation Graph (0, 0)][DBLP] DAC, 2000, pp:19-22 [Conf]
Zhao Li, C.-J. Richard Shi An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation. [Citation Graph (0, 0)][DBLP] DATE, 2005, pp:752-757 [Conf]
Zhao Li, C.-J. Richard Shi A coupled iterative/direct method for efficient time-domain simulation of nonlinear circuits with power/ground networks. [Citation Graph (0, 0)][DBLP] ISCAS (5), 2004, pp:165-168 [Conf]
Lei Yang, C.-J. Richard Shi FROSTY: A program for fast extraction of high-level structural representation from circuit description for industrial CMOS circuits. [Citation Graph (0, 0)][DBLP] Integration, 2006, v:39, n:4, pp:311-339 [Journal]
Zhao Li, C.-J. Richard Shi SILCA: SPICE-accurate iterative linear-centric analysis for efficient time-domain Simulation of VLSI circuits with strong parasitic couplings. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1087-1103 [Journal]
C.-J. Richard Shi, Sheldon X.-D. Tan Canonical symbolic analysis of large analog circuits withdeterminant decision diagrams. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:1-18 [Journal]
C.-J. Richard Shi, Sheldon X.-D. Tan Compact representation and efficient generation of s-expandedsymbolic network functions for computer-aided analog circuit design. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:7, pp:813-827 [Journal]
C.-J. Richard Shi, Michael W. Tian, Guoyong Shi Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1392-1400 [Journal]
Sheldon X.-D. Tan, C.-J. Richard Shi Hierarchical symbolic analysis of analog integrated circuits viadeterminant decision diagrams. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:4, pp:401-412 [Journal]
Sheldon X.-D. Tan, C.-J. Richard Shi Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:277-284 [Journal]
Sheldon X.-D. Tan, C.-J. Richard Shi Efficient approximation of symbolic expressions for analog behavioral modeling and analysis. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:907-918 [Journal]
C.-J. Richard Shi, Michael W. Tian Simulation and sensitivity of linear analog circuits under parameter variations by Robust interval analysis. [Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 1999, v:4, n:3, pp:280-312 [Journal]
A Graph Reduction Approach to Symbolic Circuit Analysis. [Citation Graph (, )][DBLP]
Symmetry-aware placement with transitive closure graphs for analog layout design. [Citation Graph (, )][DBLP]
Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining. [Citation Graph (, )][DBLP]
Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits. [Citation Graph (, )][DBLP]
A 6-11GHz multi-phase VCO design with active inductors. [Citation Graph (, )][DBLP]
A quantum-dot light-harvesting architecture using deterministic phase control. [Citation Graph (, )][DBLP]
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