Search the dblp DataBase

Publications of Author

1. Samar Abdi, Daniel Gajski
   On deriving equivalent architecture model from system specification. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:322-327 [Conf]
   
2. Samar Abdi, Daniel Gajski
   A formalism for functionality preserving system level transformations. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:139-144 [Conf]
   
3. Hansu Cho, Samar Abdi, Daniel Gajski
   Design and implementation of transducer for ARM-TMS communication. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2006, pp:126-127 [Conf]
   
4. Junyu Peng, Samar Abdi, Daniel Gajski
   Automatic Model Refinement for Fast Architecture Exploration. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2002, pp:332-337 [Conf]
   
5. Junyu Peng, Samar Abdi, Daniel Gajski
   A clustering technique to optimize hardware/software synchronization. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:965-968 [Conf]
   
6. Dongwan Shin, Samar Abdi, Daniel Gajski
   Automatic generation of bus functional models from transaction level models. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:756-758 [Conf]
   
7. Samar Abdi, Daniel Gajski
   Automatic generation of equivalent architecture model from functional specification. [Citation Graph (0, 0)][DBLP]
   DAC, 2004, pp:608-613 [Conf]
   
8. Samar Abdi, Dongwan Shin, Daniel Gajski
   Automatic communication refinement for system level design. [Citation Graph (0, 0)][DBLP]
   DAC, 2003, pp:300-305 [Conf]
   
9. Samar Abdi, Daniel D. Gajski
   Functional Validation of System Level Static Scheduling. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:542-547 [Conf]
   
10. Junyu Peng, Samar Abdi, Daniel Gajski
    Automatic Model Refinement for Fast Architecture Exploration. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:332-337 [Conf]
    
11. Samar Abdi, Daniel Gajski
    Verification of System Level Model Transformations. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2006, v:34, n:1, pp:29-59 [Journal]
    
12. Hansu Cho, Samar Abdi, Daniel Gajski
    Interface synthesis for heterogeneous multi-core systems from transaction level models. [Citation Graph (0, 0)][DBLP]
    LCTES, 2007, pp:140-142 [Conf]
    
13. Ines Viskic, Samar Abdi, Daniel D. Gajski
    Automatic generation of embedded communication SW for heterogeneous MPSoC platforms. [Citation Graph (0, 0)][DBLP]
    LCTES, 2007, pp:143-145 [Conf]
    
14. 
    Hardware-dependent software synthesis for many-core embedded systems. [Citation Graph (, )][DBLP]
    
    
15. 
    Cycle-approximate Retargetable Performance Estimation at the Transaction Level. [Citation Graph (, )][DBLP]
    
    
16. 
    Accurate timed RTOS model for transaction level modeling. [Citation Graph (, )][DBLP]
    
    
17. 
    Automatic SystemC TLM generation for custom communication platforms. [Citation Graph (, )][DBLP]
    
    
18. 
    Model Based Synthesis of Embedded Software. [Citation Graph (, )][DBLP]
    
    
19. 
    Automatic Generation of Cycle-Approximate TLMs with Timed RTOS Model Support. [Citation Graph (, )][DBLP]