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Daniel Gajski: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Won Kim, Daniel Gajski, David J. Kuck
    A Parallel Pipelined Relational Query Processor. [Citation Graph (3, 17)][DBLP]
    ACM Trans. Database Syst., 1984, v:9, n:2, pp:214-242 [Journal]
  2. Daniel Gajski, Won Kim, Shinya Fushimi
    A Parallel Pipelined Relational Query Processor: An Architectural Overview. [Citation Graph (2, 0)][DBLP]
    ISCA, 1984, pp:134-141 [Conf]
  3. Samar Abdi, Daniel Gajski
    On deriving equivalent architecture model from system specification. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:322-327 [Conf]
  4. Samar Abdi, Daniel Gajski
    A formalism for functionality preserving system level transformations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:139-144 [Conf]
  5. Lukai Cai, Andreas Gerstlauer, Daniel Gajski
    Multi-metric and multi-entity characterization of applications for early system design exploration. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:944-947 [Conf]
  6. Lukai Cai, Haobo Yu, Daniel Gajski
    A novel memory size model for variable-mapping in system level design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:812-817 [Conf]
  7. Hansu Cho, Samar Abdi, Daniel Gajski
    Design and implementation of transducer for ARM-TMS communication. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:126-127 [Conf]
  8. Rainer Dömer, Daniel Gajski
    Reuse and protection of intellectual property in the SpecC system. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:49-54 [Conf]
  9. Nong Fan, Viraphol Chaiyakul, Daniel Gajski
    Usage-based characterization of complex functional blocks for reuse in behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:43-48 [Conf]
  10. Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul, Shojiro Mori, Tom Nukiyama, Pierre Bricaud
    Embedded tutorial: essential issues for IP reuse. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:37-42 [Conf]
  11. Masaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura
    One language or more?: how can we design an SoC at a system level? [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:653-654 [Conf]
  12. Junyu Peng, Samar Abdi, Daniel Gajski
    Automatic Model Refinement for Fast Architecture Exploration. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:332-337 [Conf]
  13. Junyu Peng, Samar Abdi, Daniel Gajski
    A clustering technique to optimize hardware/software synchronization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:965-968 [Conf]
  14. Dongwan Shin, Samar Abdi, Daniel Gajski
    Automatic generation of bus functional models from transaction level models. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:756-758 [Conf]
  15. Haobo Yu, Rainer Dömer, Daniel Gajski
    Embedded software generation from system level design languages. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:463-468 [Conf]
  16. Jianwen Zhu, Daniel Gajski
    Compiling SpecC for simulation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:57-62 [Conf]
  17. Lukai Cai, Daniel Gajski
    Transaction level modeling: an overview. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:19-24 [Conf]
  18. Grant Martin, Daniel Gajski, David Goodwin, Patrick Lysaght, Peter Marwedel, Mike Muller, Jeff Welser
    What will system level design be when it grows up? [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:123- [Conf]
  19. Peter Marwedel, Daniel Gajski, Erwin A. de Kock, Hugo De Man, Mariagiovanna Sami, Ingemar Söderquist
    Embedded systems education: how to teach the required skills? [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:254-255 [Conf]
  20. Mehrdad Reshadi, Daniel Gajski
    A cycle-accurate compilation algorithm for custom pipelined datapaths. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:21-26 [Conf]
  21. Haobo Yu, Andreas Gerstlauer, Daniel Gajski
    RTOS scheduling in transaction level models. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:31-36 [Conf]
  22. Jianwen Zhu, Daniel Gajski
    A unified formal model of ISA and FSMD. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:121-125 [Conf]
  23. Bita Gorjiara, Mehrdad Reshadi, Pramod Chandraiah, Daniel Gajski
    Generic netlist representation for system and PE level design exploration. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:282-287 [Conf]
  24. Daniel Gajski
    Recurrence semigroups and their relation to data storage in fast recurrence solvers on parallel machines. [Citation Graph (0, 0)][DBLP]
    CONPAR, 1981, pp:343-357 [Conf]
  25. Samar Abdi, Daniel Gajski
    Automatic generation of equivalent architecture model from functional specification. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:608-613 [Conf]
  26. Samar Abdi, Dongwan Shin, Daniel Gajski
    Automatic communication refinement for system level design. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:300-305 [Conf]
  27. Smita Bakshi, Daniel Gajski
    Hardware/Software Partitioning and Pipelining. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:713-716 [Conf]
  28. Forrest Brewer, Daniel Gajski
    An expert-system paradigm for design. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:62-68 [Conf]
  29. Forrest Brewer, Daniel Gajski
    Knowledge Based Control in Micro-Architecture Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:203-209 [Conf]
  30. Lukai Cai, Andreas Gerstlauer, Daniel Gajski
    Retargetable profiling for rapid, early system-level design space exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:281-286 [Conf]
  31. Viraphol Chaiyakul, Daniel Gajski, Loganath Ramachandran
    High-Level Transformations for Minimizing Syntactic Variances. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:413-418 [Conf]
  32. Gwo-Dong Chen, Daniel Gajski
    An Intelligent Component Database for Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:150-155 [Conf]
  33. Nikil D. Dutt, Daniel Gajski
    Designer Controlled Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:754-757 [Conf]
  34. Nikil D. Dutt, Tedd Hadley, Daniel Gajski
    An Intermediate Representation for Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:14-19 [Conf]
  35. Daniel Gajski
    IP-based Design Methodology. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:43- [Conf]
  36. Daniel Gajski, Frank Vahid, Sanjiv Narayan, Jie Gong
    System-level exploration with SpecSyn. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:812-817 [Conf]
  37. Rajesh K. Gupta, Shishpal Rawat, Ingrid Verbauwhede, Gérard Berry, Ramesh Chandra, Daniel Gajski, Kris Konigsfeld, Patrick Schaumont
    Panel: The Next HDL: If C++ is the Answer, What was the Question? [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:71-72 [Conf]
  38. Chidchanok Lursinsap, Daniel Gajski
    Improving a PLA Area by Pull-Up Transistor Folding. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:608-614 [Conf]
  39. Y.-L. S. Lin, Daniel Gajski
    LES: A Layout Expert System. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:672-678 [Conf]
  40. Joseph Lis, Daniel Gajski
    VHDL Synthesis Using Structured Modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:606-609 [Conf]
  41. Sanjiv Narayan, Daniel Gajski
    Protocol Generation for Communication Channels. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:547-551 [Conf]
  42. Sanjiv Narayan, Daniel Gajski
    Interfacing Incompatible Protocols Using Interface Process Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:468-473 [Conf]
  43. Alex Orailoglu, Daniel Gajski
    Flow graph representation. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:503-509 [Conf]
  44. Roni Potasman, Joseph Lis, Alexandru Nicolau, Daniel Gajski
    Percolation Based Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:444-449 [Conf]
  45. Shishpal Rawat, William H. Joyner Jr., John A. Darringer, Daniel Gajski, Pat O. Pistilli, Hugo De Man, Carl Harris, James Solomon
    Were the good old days all that good?: EDA then and now. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:543- [Conf]
  46. Elke A. Rundensteiner, Daniel Gajski
    Functional Synthesis Using Area and Delay Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:291-296 [Conf]
  47. Frank Vahid, Daniel Gajski
    Specification Partitioning for System Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:219-224 [Conf]
  48. Jianwen Zhu, Daniel Gajski
    Soft Scheduling in High Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:219-224 [Conf]
  49. Nels Vander Zanden, Daniel Gajski
    MILO: A Microarchitecture and Logic Optimizer. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:403-408 [Conf]
  50. Lukai Cai, Daniel Gajski, Paul Kritzinger, Mike Olivarez
    Top-Down System Level Design Methodology Using SpecC, VCC and SystemC. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1137- [Conf]
  51. Daniel Gajski, Eugenio Villar, Wolfgang Rosenstiel, Vassilios Gerousis, D. Barton, J. Plantin, S. E. Ericsson, Patrizia Cavalloro, Gjalt G. de Jong
    C/C++: progress or deadlock in system-level specification. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:136-137 [Conf]
  52. Andreas Gerstlauer, Haobo Yu, Daniel Gajski
    RTOS Modeling for System Level Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10130-10135 [Conf]
  53. Heinz-Joseph Schlebusch, Gary Smith, Donatella Sciuto, Daniel Gajski, Carsten Mielenz, Christopher K. Lennard, Frank Ghenassia, Stuart Swan, Joachim Kunkel
    Transaction Based Design: Another Buzzword or the Solution to a Design Problem? [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10876-10879 [Conf]
  54. Jianwen Zhu, Daniel Gajski
    OpenJ: An Extensible System Level Design Language. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:480-484 [Conf]
  55. Jelena Trajkovic, Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski
    A Graph Based Algorithm for Data Path Optimization in Custom Processors. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:496-503 [Conf]
  56. Dai Araki, Tadatoshi Ishii, Daniel Gajski
    Rapid Prototyping with HW/SW Codesign Tool. [Citation Graph (0, 0)][DBLP]
    ECBS, 1999, pp:114-121 [Conf]
  57. Sanjiv Narayan, Daniel Gajski
    Synthesis of System-Level Bus Interfaces. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:395-399 [Conf]
  58. Loganath Ramachandran, Daniel Gajski, Viraphol Chaiyakul
    An Algorithm for Array Variable Clustering. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:262-266 [Conf]
  59. Daniel Gajski, Frank Vahid, Sanjiv Narayan
    A System-Design Methodology: Executable-Specification Refinement. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:458-463 [Conf]
  60. Nancy D. Holmes, Daniel Gajski
    An Algorithm for Generation of Behavioral Shape Functions. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:314-318 [Conf]
  61. Bita Gorjiara, Daniel Gajski
    FPGA-friendly code compression for horizontal microcoded custom IPs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2007, pp:108-115 [Conf]
  62. Hsiao-Ping Juan, Daniel Gajski, Viraphol Chaiyakul
    Clock-driven performance optimization in interactive behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:154-157 [Conf]
  63. Tsing-Fa Lee, Allen C.-H. Wu, Daniel Gajski, Youn-Long Lin
    An effective methodology for functional pipelining. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:230-233 [Conf]
  64. Sanjiv Narayan, Frank Vahid, Daniel Gajski
    System Specification and Synthesis with the SpecCharts Language. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:266-269 [Conf]
  65. Loganath Ramachandran, Daniel Gajski
    An Algorithm for Component Selection in Performance Optimized Scheduling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:92-95 [Conf]
  66. Champaka Ramachandran, Fadi J. Kurdahi, Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul
    Accurate layout area and delay modeling for system level design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:355-361 [Conf]
  67. Elke A. Rundensteiner, Daniel Gajski, Lubomir Bic
    The Component Sythesis Algorithm: Technology Mapping for Register Transfer Descriptions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:208-211 [Conf]
  68. Allen C.-H. Wu, Daniel Gajski
    Partitioning Algorithms for Layout Synthesis from Register-Transfer Netlists. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:144-147 [Conf]
  69. Frank Vahid, Daniel Gajski
    Obtaining Functionally Equivalent Simulations using VHDL and a Time-Shift Transformation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:362-365 [Conf]
  70. Allen C.-H. Wu, Viraphol Chaiyakul, Daniel Gajski
    Layout-Area Models for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:34-37 [Conf]
  71. Allen C.-H. Wu, Tedd Hadley, Daniel Gajski
    An efficient multi-view design model for real-time interactive synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:328-331 [Conf]
  72. Rajesh K. Gupta, Daniel Gajski, Randy Allen, Yatin Trivedi
    Opportunities and pitfalls in HDL-based system design. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:56-0 [Conf]
  73. Daniel Gajski, David J. Kuck, Duncan H. Lawrie, Ahmed H. Sameh
    Cedar : A Large Scale Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ICPP, 1983, pp:524-529 [Conf]
  74. Jih-Kwon Peir, Daniel Gajski
    CAMP: A Programming Aide for Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:475-482 [Conf]
  75. Min-You Wu, Daniel Gajski
    Hypertool: A Programming Aid for Multicomputers. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1989, pp:15-18 [Conf]
  76. Daniel Gajski, Nikil D. Dutt
    Benchmarking and the Art of Syntesis Tool Comparison. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:439-453 [Conf]
  77. Daniel Gajski, Rainer Dömer, Jianwen Zhu
    IP-Centric Methodology and Specification Language. [Citation Graph (0, 0)][DBLP]
    DIPES, 1998, pp:3-22 [Conf]
  78. Achim Rettberg, Franz J. Rammig, Andreas Gerstlauer, Daniel Gajski, Wolfram Hardt, Bernd Kleinjohann
    The Specification Language SpecC within the PARADISE Design Environment. [Citation Graph (0, 0)][DBLP]
    DIPES, 2000, pp:111-120 [Conf]
  79. Utpal Banerjee, Daniel Gajski
    Fast Execution of Loops With IF Statements. [Citation Graph (0, 0)][DBLP]
    ISCA, 1984, pp:126-132 [Conf]
  80. Lukai Cai, Daniel Gajski, Mike Olivarez
    Introduction of system level architecture exploration using the SpecC methodology. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:9-12 [Conf]
  81. Shuqing Zhao, Daniel Gajski
    Modeling a new RTL semantics in C++. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:741-744 [Conf]
  82. Brian Bailey, Daniel Gajski
    RTL semantics and methodology. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:69-74 [Conf]
  83. Smita Bakshi, Daniel Gajski
    A Scheduling and Pipelining Algorithm for Hardware/Software Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 1997, pp:113-0 [Conf]
  84. Daniel Gajski, Reinaldo A. Bergamaschi
    Panel Statement. [Citation Graph (0, 0)][DBLP]
    ISSS, 1999, pp:8-9 [Conf]
  85. Daniel Gajski, Andreas Gerstlauer
    System-Level Abstraction Semantics. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:231-236 [Conf]
  86. Daniel Gajski, Junyu Peng
    Optimal Message-Passing for Data Coherency in Distributed Architecture. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:20-25 [Conf]
  87. Daniel Gajski
    System design extreme makeover. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2005, pp:71-75 [Conf]
  88. Min-You Wu, Daniel Gajski
    A Programming Aid for Message-passing Systems. [Citation Graph (0, 0)][DBLP]
    PPSC, 1987, pp:328-332 [Conf]
  89. Junyu Peng, Samar Abdi, Daniel Gajski
    Automatic Model Refinement for Fast Architecture Exploration. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:332-337 [Conf]
  90. Daniel Gajski, Robert H. Kuhn
    New VLSI Tools - Guest Editors' Introduction. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1983, v:16, n:12, pp:11-14 [Journal]
  91. Daniel Gajski, Jih-Kwon Peir
    Essential Issues in Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1985, v:18, n:6, pp:9-27 [Journal]
  92. Daniel Gajski, David A. Padua, David J. Kuck, Robert H. Kuhn
    A Second Opinion on Data Flow Machines and Languages. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1982, v:15, n:2, pp:58-69 [Journal]
  93. Samar Abdi, Daniel Gajski
    Verification of System Level Model Transformations. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2006, v:34, n:1, pp:29-59 [Journal]
  94. Daniel Gajski, Jih-Kwon Peir
    Comparison of five multiprocessor systems. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1985, v:2, n:3, pp:265-282 [Journal]
  95. Jacob A. Abraham, Daniel Gajski
    Design of Testable Structures Defined by Simple Loops. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:11, pp:875-884 [Journal]
  96. Utpal Banerjee, Daniel Gajski
    Fast Execution of Loops with IF Statements. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:11, pp:1030-1033 [Journal]
  97. Avinoam Bilgory, Daniel Gajski
    A Heuristic for Suffix Solutions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:1, pp:34-42 [Journal]
  98. Daniel Gajski
    Parallel Compressors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:5, pp:393-398 [Journal]
  99. Daniel Gajski
    An Algorithm for Solving Linear Recurrence Systems on Parallel and Pipelined Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:3, pp:190-206 [Journal]
  100. Smita Bakshi, Daniel Gajski
    Performance-constrained hierarchical pipelining for behaviors, loops, and operations. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:1, pp:1-25 [Journal]
  101. Jie Gong, Daniel Gajski, Smita Bakshi
    Model refinement for hardware-software codesign. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:1, pp:22-41 [Journal]
  102. En-Shou Chang, Daniel Gajski, Sanjiv Narayan
    An optimal clock period selection method based on slack minimization criteria. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1996, v:1, n:3, pp:352-370 [Journal]
  103. Min-You Wu, Daniel Gajski
    Hypertool: A Programming Aid for Message-Passing Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1990, v:1, n:3, pp:330-343 [Journal]
  104. Mehrdad Reshadi, Daniel Gajski
    Interrupt and low-level programming support for expanding the application domain of statically-scheduled horizontal-microcoded architectures in embedded systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1337-1342 [Conf]
  105. Hansu Cho, Samar Abdi, Daniel Gajski
    Interface synthesis for heterogeneous multi-core systems from transaction level models. [Citation Graph (0, 0)][DBLP]
    LCTES, 2007, pp:140-142 [Conf]
  106. Jelena Trajkovic, Daniel Gajski
    Automatic Data Path Generation from C code for Custom Processors. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:107-120 [Conf]

  107. Hardware-dependent software synthesis for many-core embedded systems. [Citation Graph (, )][DBLP]

  108. Automatic architecture refinement techniques for customizing processing elements. [Citation Graph (, )][DBLP]

  109. Specify-explore-refine (SER): from specification to implementation. [Citation Graph (, )][DBLP]

  110. C-based design flow: a case study on G.729A for voice over internet protocol (VoIP). [Citation Graph (, )][DBLP]

  111. Cycle-approximate Retargetable Performance Estimation at the Transaction Level. [Citation Graph (, )][DBLP]

  112. A new algorithm for transistor sizing in CMOS circuits. [Citation Graph (, )][DBLP]

  113. Silicon compilation of switched: capacitor networks. [Citation Graph (, )][DBLP]

  114. A novel profile-driven technique for simultaneous power and code-size optimization of microcoded IPs. [Citation Graph (, )][DBLP]

  115. Aspect-Oriented Architecture Description for Retargetable Compilation, Simulation and Synthesis of Application-Specific Pipelined Datapaths . [Citation Graph (, )][DBLP]

  116. Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications. [Citation Graph (, )][DBLP]

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