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Elaheh Bozorgzadeh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Elaheh Bozorgzadeh, Seda Ogrenci Memik, Majid Sarrafzadeh
    RPack: routability-driven packing for cluster-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:629-634 [Conf]
  2. Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt
    PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:491-496 [Conf]
  3. Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
    Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:335-340 [Conf]
  4. Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh
    Optimal integer delay budgeting on directed acyclic graphs. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:920-925 [Conf]
  5. Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh
    Creating and Exploiting Flexibility in Steiner Trees. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:195-198 [Conf]
  6. Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane
    Floorplan-aware automated synthesis of bus-based communication architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:565-570 [Conf]
  7. Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh
    Incremental Timing Budget Management in Programmable Systems. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:240-246 [Conf]
  8. Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
    Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:273-274 [Conf]
  9. S. Dai, E. Bozorgzadeh
    CAD Tool for FPGAs with Embedded Hard Cores for Design Space Exploration of Future Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:329-330 [Conf]
  10. Elaheh Bozorgzadeh, Majid Sarrafzadeh
    Customized regular channel design in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:240- [Conf]
  11. Soheil Ghiasi, Karlene Nguyen, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    On computation and resource management in an FPGA-based computation environment. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:243- [Conf]
  12. Soheil Ghiasi, Elaheh Bozorgzadeh, Siddharth Choudhuri, Majid Sarrafzadeh
    A unified theory of timing budget management. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:653-659 [Conf]
  13. Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    Predictable Routing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:110-113 [Conf]
  14. Ryan Kastner, Seda Ogrenci Memik, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    Instruction Generation for Hybrid Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:127-0 [Conf]
  15. Seda Ogrenci Memik, Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh
    A Super-Scheduler for Embedded Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:391-0 [Conf]
  16. Love Singhal, Elaheh Bozorgzadeh
    Fast timing closure by interconnect criticality driven delay relaxation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:792-797 [Conf]
  17. L. Singhal, E. Bozorgzadeh
    Physically-aware exploitation of component reuse in a partially reconfigurable architecture. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  18. Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    An exact algorithm for coupling-free routing. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:10-15 [Conf]
  19. Majid Sarrafzadeh, Elaheh Bozorgzadeh, Ryan Kastner, Ankur Srivastava
    Design and analysis of physical design algorithms. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:82-89 [Conf]
  20. Xiaojian Yang, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    Wirelength estimation based on rent exponents of partitioning and placement. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:25-31 [Conf]
  21. Chunhong Chen, Elaheh Bozorgzadeh, Ankur Srivastava, Majid Sarrafzadeh
    Budget Management with Applications. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 2002, v:34, n:3, pp:261-275 [Journal]
  22. Elaheh Bozorgzadeh, Seda Ogrenci Memik, Xiaojian Yang, Majid Sarrafzadeh
    Routability-Driven Packing: Metrics And Algorithms For Cluster-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2004, v:13, n:1, pp:77-100 [Journal]
  23. Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh
    Optimal integer delay-budget assignment on directed acyclic graphs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1184-1199 [Journal]
  24. Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh
    Creating and exploiting flexibility in rectilinear Steiner trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:605-615 [Journal]
  25. Soheil Ghiasi, Elaheh Bozorgzadeh, Po-Kuan Huang, Roozbeh Jafari, Majid Sarrafzadeh
    A Unified Theory of Timing Budget Management. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2364-2375 [Journal]
  26. Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    Pattern routing: use and theory for increasing predictability andavoiding coupling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:777-790 [Journal]
  27. Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Elaheh Bozorgzadeh
    Statistical Analysis and Design of HARP FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2088-2102 [Journal]
  28. Ryan Kastner, Adam Kaplan, Seda Ogrenci Memik, Elaheh Bozorgzadeh
    Instruction generation for hybrid reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:4, pp:605-627 [Journal]
  29. Seda Ogrenci Memik, Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    A scheduling algorithm for optimization and early planning in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:1, pp:33-57 [Journal]
  30. Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane
    FABSYN: floorplan-aware bus architecture synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:3, pp:241-253 [Journal]
  31. S. Golshan, E. Bozorgzadeh
    Single-Event-Upset (SEU) Awareness in FPGA Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:330-333 [Conf]
  32. Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt, Juanjo Noguera
    Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:771-776 [Conf]
  33. Love Singhal, Elaheh Bozorgzadeh
    Multi-layer Floorplanning on a Sequence of Reconfigurable Designs. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-8 [Conf]
  34. Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt
    Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1189-1202 [Journal]
  35. Soheil Ghiasi, Elaheh Bozorgzadeh, Karlene Nguyen, Majid Sarrafzadeh
    Efficient Timing Budget Management for Accuracy Improvement in a Collaborative Object Tracking System. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:42, n:1, pp:43-55 [Journal]

  36. Transition-aware real-time task scheduling for reconfigurable embedded systems. [Citation Graph (, )][DBLP]


  37. Heterogeneous Floorplanner for FPGA. [Citation Graph (, )][DBLP]


  38. Novel Multi-Layer floorplanning for Heterogeneous FPGAs. [Citation Graph (, )][DBLP]


  39. Process variation aware system-level task allocation using stochastic ordering of delay distributions. [Citation Graph (, )][DBLP]


  40. Energy-aware co-processor selection for embedded processors on FPGAs. [Citation Graph (, )][DBLP]


  41. Seamless sequence of software defined radio designs through hardware reconfigurability of FPGAs. [Citation Graph (, )][DBLP]


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