The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Seda Ogrenci Memik: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Elaheh Bozorgzadeh, Seda Ogrenci Memik, Majid Sarrafzadeh
    RPack: routability-driven packing for cluster-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:629-634 [Conf]
  2. Somsubhra Mondal, Seda Ogrenci Memik
    Resource sharing in pipelined CDFG synthesis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:795-798 [Conf]
  3. Rajarshi Mukherjee, Seda Ogrenci Memik
    Evaluation of dual VDD fabrics for low power FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1240-1243 [Conf]
  4. Seda Ogrenci Memik, Gokhan Memik, Roozbeh Jafari, Eren Kursun
    Global resource sharing for synthesis of control data flow graphs on FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:604-609 [Conf]
  5. Rajarshi Mukherjee, Seda Ogrenci Memik
    Systematic temperature sensor allocation and placement for microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:542-547 [Conf]
  6. Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Memik
    Temperature-aware resource allocation and binding in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:196-201 [Conf]
  7. Rajarshi Mukherjee, Somsubhra Mondal, Seda Ogrenci Memik
    A Sensor Distribution Algorithm for FPGAs with Minimal Dynamic Reconfiguration Overhead. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:56-62 [Conf]
  8. Rajarshi Mukherjee, Seda Ogrenci Memik
    Power Management for FPGAs: Power-Driven Design Partitioning. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:326-327 [Conf]
  9. Gokhan Memik, Seda Ogrenci Memik, William H. Mangione-Smith
    Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:131-0 [Conf]
  10. Somsubhra Mondal, Seda Ogrenci Memik, Nikolaos Bellas
    Pre-synthesis Queue Size Estimation of Streaming Data Flow Graphs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:325-326 [Conf]
  11. Somsubhra Mondal, Seda Ogrenci Memik, Debasish Das
    Hierarchical LUT structures for leakage power reduction (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:272- [Conf]
  12. Rajarshi Mukherjee, Seda Ogrenci Memik
    Power-Driven Design Partitioning. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:740-750 [Conf]
  13. David Nguyen, Gokhan Memik, Seda Ogrenci Memik, Alok N. Choudhary
    Real-Time Feature Extraction for High Speed Networks. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:438-443 [Conf]
  14. Somsubhra Mondal, Seda Ogrenci Memik
    Fine-grain leakage optimization in SRAM based FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:238-243 [Conf]
  15. Ryan Kastner, Seda Ogrenci Memik, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    Instruction Generation for Hybrid Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:127-0 [Conf]
  16. Seda Ogrenci Memik, Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh
    A Super-Scheduler for Embedded Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:391-0 [Conf]
  17. Ankur Srivastava, Seda Ogrenci Memik, Bo-Kyung Choi, Majid Sarrafzadeh
    Achieving Design Closure Through Delay Relaxation Parameter. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:54-57 [Conf]
  18. Min Ni, Seda Ogrenci Memik
    Thermal-induced leakage power optimization by redundant resource allocation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:297-302 [Conf]
  19. Rajarshi Mukherjee, Somsubhra Mondal, Seda Ogrenci Memik
    Thermal sensor allocation and placement for reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:437-442 [Conf]
  20. Rajarshi Mukherjee, Seda Ogrenci Memik
    Physical aware frequency selection for dynamic thermal management in multi-core systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:547-552 [Conf]
  21. Seda Ogrenci Memik, Farzan Fallah
    Accelerated SAT-based Scheduling of Control/Data Flow Graphs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:395-0 [Conf]
  22. Roozbeh Jafari, Seda Ogrenci Memik, Majid Sarrafzadeh
    Quick Reconfiguration in Clustered Micro-Sequencer. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  23. Somsubhra Mondal, Seda Ogrenci Memik
    A low power FPGA routing architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1222-1225 [Conf]
  24. Eren Kursun, Ankur Srivastava, Seda Ogrenci Memik, Majid Sarrafzadeh
    Early evaluation techniques for low power binding. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:160-165 [Conf]
  25. Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Memik
    Peak temperature control and leakage reduction during binding in high level synthesis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:251-256 [Conf]
  26. Elaheh Bozorgzadeh, Seda Ogrenci Memik, Xiaojian Yang, Majid Sarrafzadeh
    Routability-Driven Packing: Metrics And Algorithms For Cluster-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2004, v:13, n:1, pp:77-100 [Journal]
  27. Seda Ogrenci Memik, Aggelos K. Katsaggelos, Majid Sarrafzadeh
    Analysis and FPGA Implementation of Image Restoration under Resource Constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:3, pp:390-399 [Journal]
  28. Ankur Srivastava, Seda Ogrenci Memik, Bo-Kyung Choi, Majid Sarrafzadeh
    On effective slack management in postscheduling phase. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:645-653 [Journal]
  29. Ryan Kastner, Adam Kaplan, Seda Ogrenci Memik, Elaheh Bozorgzadeh
    Instruction generation for hybrid reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:4, pp:605-627 [Journal]
  30. Seda Ogrenci Memik, Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    A scheduling algorithm for optimization and early planning in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:1, pp:33-57 [Journal]
  31. Min Ni, Seda Ogrenci Memik
    Self-heating-aware optimal wire sizing under Elmore delay model. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1373-1378 [Conf]
  32. Somsubhra Mondal, Seda Ogrenci Memik
    Power Optimization Techniques for SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-2 [Conf]
  33. Somsubhra Mondal, Seda Ogrenci Memik, Nikolaos Bellas
    Pre-Synthesis Area Estimation of Reconfigurable Streaming Accelerators. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  34. Somsubhra Mondal, Rajarshi Mukherjee, Seda Ogrenci Memik
    Fine-grain thermal profiling and sensor insertion for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  35. Rajarshi Mukherjee, Seda Ogrenci Memik
    An Integrated Approach to Thermal Management in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1165-1174 [Journal]
  36. Eren Kursun, Rajarshi Mukherjee, Seda Ogrenci Memik
    Early Quality Assessment for Low Power Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:3, pp:273-285 [Journal]

  37. Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction. [Citation Graph (, )][DBLP]


  38. A power and temperature aware DRAM architecture. [Citation Graph (, )][DBLP]


  39. Automated design of self-adjusting pipelines. [Citation Graph (, )][DBLP]


  40. A framework for optimizing thermoelectric active cooling systems. [Citation Graph (, )][DBLP]


  41. Optimization of the bias current network for accurate on-chip thermal monitoring. [Citation Graph (, )][DBLP]


  42. Optimization of an on-chip active cooling system based on thin-film thermoelectric coolers. [Citation Graph (, )][DBLP]


  43. Inversed Temperature Dependence aware clock skew scheduling for sequential circuits. [Citation Graph (, )][DBLP]


  44. Using Speculative Functional Units in high level synthesis. [Citation Graph (, )][DBLP]


  45. FPGA Implementation of the Interior-Point Algorithm with Applications to Collision Detection. [Citation Graph (, )][DBLP]


  46. Towards an "early neural circuit simulator": A FPGA implementation of processing in the rat whisker system. [Citation Graph (, )][DBLP]


  47. A self-adjusting clock tree architecture to cope with temperature variations. [Citation Graph (, )][DBLP]


  48. A novel SoC design methodology combining adaptive software and reconfigurable hardware. [Citation Graph (, )][DBLP]


  49. Early planning for clock skew scheduling during register binding. [Citation Graph (, )][DBLP]


  50. An approach for adaptive DRAM temperature and power management. [Citation Graph (, )][DBLP]


  51. An O(nlogn) edge-based algorithm for obstacle-avoiding rectilinear steiner tree construction. [Citation Graph (, )][DBLP]


  52. A revisit to the primal-dual based clock skew scheduling algorithm. [Citation Graph (, )][DBLP]


  53. Adaptive Metrics for System-Level Functional Partitioning. [Citation Graph (, )][DBLP]


  54. An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-dimensional Reconfigurable Architectures. [Citation Graph (, )][DBLP]


  55. A Reconfiguration-Aware Floorplacer for FPGAs. [Citation Graph (, )][DBLP]


Search in 0.017secs, Finished in 0.019secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002