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Publications of Author

1. Lisane B. de Brisolara, Leandro Buss Becker, Luigi Carro, Flávio Rech Wagner, Carlos Eduardo Pereira, Ricardo Reis
   Comparing high-level modeling approaches for embedded system design. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:986-989 [Conf]
   
2. Ricardo Reis, Fernanda Lima Kastensmidt, José Luís Almada Güntzel
   Physical design methodologies for performance predictability and manufacturability. [Citation Graph (0, 0)][DBLP]
   Conf. Computing Frontiers, 2004, pp:390-397 [Conf]
   
3. Fernanda Lima Kastensmidt, Gustavo Neuberger, Luigi Carro, Ricardo Reis
   Designing and testing fault-tolerant techniques for SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
   Conf. Computing Frontiers, 2004, pp:419-432 [Conf]
   
4. Alex Panato, Sandro V. Silva, Flávio Rech Wagner, Marcelo O. Johann, Ricardo Reis, Sergio Bampi
   Design of Very Deep Pipelined Multipliers for FPGAs. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:52-57 [Conf]
   
5. Ricardo Reis
   Requirements for Computer-Aided Learning from the Point of View of Electronic Design. [Citation Graph (0, 0)][DBLP]
   EDUTECH, 2004, pp:63-68 [Conf]
   
6. Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis
   Design of a Robust 8-Bit Microprocessor to Soft Errors. [Citation Graph (0, 0)][DBLP]
   IOLTS, 2006, pp:195-196 [Conf]
   
7. Renato Fernandes Hentschke, Ricardo Reis
   Plic-Plac: a novel constructive algorithm for placement. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2003, pp:461-464 [Conf]
   
8. Claudio Menezes, Cristina Meinhardt, Ricardo Reis, Reginaldo Tavares
   A Regular Layout Approach for ASICs. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2006, pp:424-425 [Conf]
   
9. Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis
   3D-Vias Aware Quadratic Placement for 3D VLSI Circuits. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2007, pp:67-72 [Conf]
   
10. Daniel Lima Ferrão, Ricardo Reis, José Luís Almada Güntzel
    Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:301-310 [Conf]
    
11. Fabricio B. Bastian, Cristiano Lazzari, José Luís Almada Güntzel, Ricardo Reis
    A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:732-741 [Conf]
    
12. Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis
    Designing Low-Power Embedded Software for Mass-Produced Microprocessor by Using a Loop Table in On-Chip Memory. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:59-68 [Conf]
    
13. Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis
    Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gates. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:196-201 [Conf]
    
14. Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis
    Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:220-225 [Conf]
    
15. Cristiano Santos, Gustavo Wilke, Cristiano Lazzari, Ricardo Reis, José Luís Almada Güntzel
    A Transistor Sizing Method Applied to an Automatic Layout Generation Tool. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:303-0 [Conf]
    
16. Fernanda Lima Kastensmidt, Gustavo Neuberger, Renato Fernandes Hentschke, Luigi Carro, Ricardo Reis
    Designing Fault-Tolerant Techniques for SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:6, pp:552-562 [Journal]
    
17. Gustavo Neuberger, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis
    An Automatic Technique for Optimizing Reed-Solomon Codes to Improve Fault Tolerance in Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:1, pp:50-58 [Journal]
    
18. João Leonardo Fragoso, Eduardo Costa Pereira, Juergen Rochol, Sergio Bampi, Ricardo Reis
    Specification and design of an Ethernet Interface soft IP. [Citation Graph (0, 0)][DBLP]
    J. Braz. Comp. Soc., 2000, v:6, n:3, pp:5-12 [Journal]
    
19. Fernanda Lima Kastensmidt, Gustavo Neuberger, Luigi Carro, Ricardo Reis
    Desenvolvimento de Técnicas de Tolerância à Falhas para Componentes Programáveis por SRAM. [Citation Graph (0, 0)][DBLP]
    RITA, 2005, v:12, n:1, pp:47-60 [Journal]
    
20. Renato Fernandes Hentschke, Ricardo Reis
    A 3D-Via Legalization Algorithm for 3D VLSI Circuits and its Impact on Wire Length. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2036-2039 [Conf]
    
21. Cristiano Lazzari, Lorena Anghel, Ricardo Reis
    A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:331-344 [Conf]
    
22. 
    Non-uniform clock mesh optimization with linear programming buffer insertion. [Citation Graph (, )][DBLP]
    
    
23. 
    A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips. [Citation Graph (, )][DBLP]
    
    
24. 
    An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs. [Citation Graph (, )][DBLP]
    
    
25. 
    Built-in aging monitoring for safety-critical applications. [Citation Graph (, )][DBLP]
    
    
26. 
    Comparing transient-fault effects on synchronous and on asynchronous circuits. [Citation Graph (, )][DBLP]
    
    
27. 
    Design procedure for DVB-T receivers large tuning range LP filter. [Citation Graph (, )][DBLP]
    
    
28. 
    A New Clock Mesh Buffer Sizing Methodology for Skew and Power Reduction. [Citation Graph (, )][DBLP]
    
    
29. 
    Cell placement on graphics processing units. [Citation Graph (, )][DBLP]
    
    
30. 
    A novel scheme to reduce short-circuit power in mesh-based clock architectures. [Citation Graph (, )][DBLP]
    
    
31. 
    Protecting digital circuits against hold time violation due to process variability. [Citation Graph (, )][DBLP]
    
    
32. 
    Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC. [Citation Graph (, )][DBLP]
    
    
33. 
    Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies. [Citation Graph (, )][DBLP]
    
    
34. 
    Efficient timing closure with a transistor level design flow. [Citation Graph (, )][DBLP]
    
    
35. 
    Structuring Web course pages as Automata: revising concepts. [Citation Graph (, )][DBLP]