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Kanak Agarwal:
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Publications of Author
- Mridul Agarwal, Kanak Agarwal, Dennis Sylvester, David Blaauw
Statistical modeling of cross-coupling effects in VLSI interconnects. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:503-506 [Conf]
- Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu
Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2002, pp:77-86 [Conf]
- Kanak Agarwal, Dennis Sylvester, David Blaauw
A simplified transmission-line based crosstalk noise model for on-chip RLC wiring. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2004, pp:858-864 [Conf]
- Kanak Agarwal, Dennis Sylvester, David Blaauw, Anirudh Devgan
Achieving continuous VT performance in a dual VT process. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:393-398 [Conf]
- Kanak Agarwal, Sani R. Nassif
Statistical analysis of SRAM cell stability. [Citation Graph (0, 0)][DBLP] DAC, 2006, pp:57-62 [Conf]
- Kanak Agarwal, Dennis Sylvester, David Blaauw
An effective capacitance based driver output model for on-chip RLC interconnects. [Citation Graph (0, 0)][DBLP] DAC, 2003, pp:376-381 [Conf]
- Kanak Agarwal, Dennis Sylvester, David Blaauw
Simple metrics for slew rate of RC circuits based on two circuit moments. [Citation Graph (0, 0)][DBLP] DAC, 2003, pp:950-953 [Conf]
- Kanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula
Variational delay metrics for interconnect timing analysis. [Citation Graph (0, 0)][DBLP] DAC, 2004, pp:381-384 [Conf]
- Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David Blaauw, Stephen W. Director
Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. [Citation Graph (0, 0)][DBLP] DAC, 2005, pp:535-540 [Conf]
- Shidhartha Das, Kanak Agarwal, David Blaauw, Dennis Sylvester
Optimal Inductance for On-chip RLC Interconnections. [Citation Graph (0, 0)][DBLP] ICCD, 2003, pp:264-0 [Conf]
- Saumil Shah, Kanak Agarwal, Dennis Sylvester
A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters. [Citation Graph (0, 0)][DBLP] ICCD, 2004, pp:138-143 [Conf]
- Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif
Power-aware global signaling strategies. [Citation Graph (0, 0)][DBLP] ISCAS (1), 2005, pp:604-607 [Conf]
- Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif
Approaches to run-time and standby mode leakage reduction in global buses. [Citation Graph (0, 0)][DBLP] ISLPED, 2004, pp:188-193 [Conf]
- Kanak Agarwal, Kevin J. Nowka, Harmander Deogun, Dennis Sylvester
Power Gating with Multiple Sleep Modes. [Citation Graph (0, 0)][DBLP] ISQED, 2006, pp:633-637 [Conf]
- Rahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown
Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. [Citation Graph (0, 0)][DBLP] ISQED, 2005, pp:284-290 [Conf]
- Kanak Agarwal, Kevin J. Nowka
Dynamic Power Management by Combination of Dual Static Supply Voltages. [Citation Graph (0, 0)][DBLP] ISQED, 2007, pp:85-92 [Conf]
- Kanak Agarwal, Dennis Sylvester, David Blaauw
A library compatible driving point model for on-chip RLC interconnects. [Citation Graph (0, 0)][DBLP] Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:63-69 [Conf]
- Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu
Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. [Citation Graph (0, 0)][DBLP] VLSI Design, 2002, pp:77-0 [Conf]
- Kanak Agarwal, Mridul Agarwal, Dennis Sylvester, David Blaauw
Statistical interconnect metrics for physical-design optimization. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1273-1288 [Journal]
- Kanak Agarwal, Dennis Sylvester, David Blaauw
A library compatible driver output model for on-chip RLC transmission lines. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:128-136 [Journal]
- Kanak Agarwal, Dennis Sylvester, David Blaauw
A simple metric for slew rate of RC circuits based on two circuit moments. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1346-1354 [Journal]
- Kanak Agarwal, Dennis Sylvester, David Blaauw
Modeling and analysis of crosstalk noise in coupled RLC interconnects. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:892-901 [Journal]
- Takashi Sato, Yu Cao, Kanak Agarwal, Dennis Sylvester, Chenming Hu
Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:560-572 [Journal]
- Kanak Agarwal, Sani R. Nassif
Characterizing Process Variation in Nanometer CMOS. [Citation Graph (0, 0)][DBLP] DAC, 2007, pp:396-399 [Conf]
- Emrah Acar, Kanak Agarwal, Sani R. Nassif
Characterization of total chip leakage using inverse (reciprocal) gamma distribution. [Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf]
- Sani R. Nassif, Kanak Agarwal, Emrah Acar
Methods for estimating decoupling capacitance of nonswitching circuit blocks. [Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf]
- H. Singh, Kanak Agarwal, Dennis Sylvester, Kevin J. Nowka
Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1215-1224 [Journal]
- Kanak Agarwal, Rahul M. Rao, Dennis Sylvester, Richard B. Brown
Parametric Yield Analysis and Optimization in Leakage Dominated Technologies. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:613-623 [Journal]
Leakage power reduction using stress-enhanced layouts. [Citation Graph (, )][DBLP]
Closed-form modeling of layout-dependent mechanical stress. [Citation Graph (, )][DBLP]
Frequency domain decomposition of layouts for double dipole lithography. [Citation Graph (, )][DBLP]
On-die sensors for measuring process and environmental variations in integrated circuits. [Citation Graph (, )][DBLP]
Efficient computation of current flow in signal wires for reliability analysis. [Citation Graph (, )][DBLP]
Characterizing within-die variation from multiple supply port IDDQ measurements. [Citation Graph (, )][DBLP]
Stress aware layout optimization. [Citation Graph (, )][DBLP]
A Design Model for Random Process Variability. [Citation Graph (, )][DBLP]
The impact of BEOL lithography effects on the SRAM cell performance and yield. [Citation Graph (, )][DBLP]
Simultaneous extraction of effective gate length and low-field mobility in non-uniform devices. [Citation Graph (, )][DBLP]
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