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Title:
Author:
Dennis Sylvester: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mridul Agarwal, Kanak Agarwal, Dennis Sylvester, David Blaauw
    Statistical modeling of cross-coupling effects in VLSI interconnects. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:503-506 [Conf]
  2. Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu
    Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:77-86 [Conf]
  3. Kanak Agarwal, Dennis Sylvester, David Blaauw
    A simplified transmission-line based crosstalk noise model for on-chip RLC wiring. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:858-864 [Conf]
  4. Kanak Agarwal, Dennis Sylvester, David Blaauw, Anirudh Devgan
    Achieving continuous VT performance in a dual VT process. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:393-398 [Conf]
  5. Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown
    Process-induced skew reduction in nominal zero-skew clock trees. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:84-89 [Conf]
  6. Sarvesh H. Kulkarni, Dennis Sylvester
    Power distribution techniques for dual VDD circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:838-843 [Conf]
  7. Dongwoo Lee, David Blaauw, Dennis Sylvester
    Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:399-404 [Conf]
  8. Kanak Agarwal, Dennis Sylvester, David Blaauw
    An effective capacitance based driver output model for on-chip RLC interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:376-381 [Conf]
  9. Kanak Agarwal, Dennis Sylvester, David Blaauw
    Simple metrics for slew rate of RC circuits based on two circuit moments. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:950-953 [Conf]
  10. Kanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula
    Variational delay metrics for interconnect timing analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:381-384 [Conf]
  11. Andrew E. Caldwell, Yu Cao, Andrew B. Kahng, Farinaz Koushanfar, Hua Lu, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester
    GTX: the MARCO GSRC technology extrapolation system. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:693-698 [Conf]
  12. Luigi Capodieci, Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang
    Toward a methodology for manufacturability-driven design rule exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:311-316 [Conf]
  13. Harmander Deogun, Rajeev R. Rao, Dennis Sylvester, David Blaauw
    Leakage-and crosstalk-aware bus encoding for total power reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:779-782 [Conf]
  14. Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester
    Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:365-368 [Conf]
  15. Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester
    Selective gate-length biasing for cost-effective runtime leakage control. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:327-330 [Conf]
  16. Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang
    A cost-driven lithographic correction methodology based on off-the-shelf sizing tools. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:16-21 [Conf]
  17. Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown
    Clock buffer and wire sizing using sequential programming. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1041-1046 [Conf]
  18. Eric Karl, David Blaauw, Dennis Sylvester, Trevor N. Mudge
    Reliability modeling and management in dynamic microprocessor-based systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1057-1060 [Conf]
  19. Dongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester
    Analysis and minimization techniques for total leakage considering gate oxide leakage. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:175-180 [Conf]
  20. Sani R. Nassif, Vijay Pitchumani, N. Rodriguez, Dennis Sylvester, Clive Bittlestone, Riko Radojcic
    Variation-aware analysis: savior of the nanometer era? [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:411-412 [Conf]
  21. Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni
    Pushing ASIC performance in a power envelope. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:788-793 [Conf]
  22. Jan M. Rabaey, Dennis Sylvester, David Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang
    Reshaping EDA for power. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:15- [Conf]
  23. Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester
    Parametric yield estimation considering leakage variability. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:442-447 [Conf]
  24. Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David Blaauw, Stephen W. Director
    Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:535-540 [Conf]
  25. Ashish Srivastava, Dennis Sylvester, David Blaauw
    Statistical optimization of leakage power considering process variations using dual-Vth and sizing. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:773-778 [Conf]
  26. Ashish Srivastava, Dennis Sylvester, David Blaauw
    Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:783-787 [Conf]
  27. Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar
    Tradeoffs between date oxide leakage and delay for dual Tox circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:761-766 [Conf]
  28. Dennis Sylvester, Himanshu Kaul
    Future Performance Challenges in Nanometer Design. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:3-8 [Conf]
  29. Jie Yang, Luigi Capodieci, Dennis Sylvester
    Advanced timing analysis based on post-OPC extraction of critical dimensions. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:359-364 [Conf]
  30. Bo Zhai, David Blaauw, Dennis Sylvester, Krisztián Flautner
    Theoretical and practical limits of dynamic voltage scaling. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:868-873 [Conf]
  31. Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylvester, Trevor N. Mudge
    Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:650-651 [Conf]
  32. Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin
    DVS for On-Chip Bus Designs Based on Timing Error Correction. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:80-85 [Conf]
  33. Dongwoo Lee, Harmander Deogun, David Blaauw, Dennis Sylvester
    Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:494-499 [Conf]
  34. Rajeev R. Rao, Kaviraj Chopra, David Blaauw, Dennis Sylvester
    An efficient static algorithm for computing the soft error rates of combinational circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:164-169 [Conf]
  35. Ashish Srivastava, Dennis Sylvester, David Blaauw
    Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:718-719 [Conf]
  36. Robert Bai, Nam Sung Kim, Dennis Sylvester, Trevor N. Mudge
    Total leakage optimization strategies for multi-level caches. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:381-384 [Conf]
  37. Matthew R. Guthaus, Natesan Venkateswaran, Vladimir Zolotov, Dennis Sylvester, Richard B. Brown
    Optimization objectives and models of variation for statistical gate sizing. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:313-316 [Conf]
  38. Himanshu Kaul, Dennis Sylvester
    A novel buffer circuit for energy efficient signaling in dual-VDD systems. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:462-467 [Conf]
  39. Himanshu Kaul, Dennis Sylvester, David Blaauw
    Active shields: a new approach to shielding global wires. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:112-117 [Conf]
  40. Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester
    Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:56-61 [Conf]
  41. Yu Cao, Xiao-Dong Yang, Xuejue Huang, Dennis Sylvester
    Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:848-854 [Conf]
  42. Kaviraj Chopra, Saumil Shah, Ashish Srivastava, David Blaauw, Dennis Sylvester
    Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:1023-1028 [Conf]
  43. Saumil Shah, Ashish Srivastava, Dushyant Sharma, Dennis Sylvester, David Blaauw, Vladimir Zolotov
    Discrete Vt assignment and gate sizing using a self-snapping continuous formulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:705-712 [Conf]
  44. Ashish Srivastava, Dennis Sylvester
    A general framework for probabilistic low-power design space exploration considering process variation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:808-813 [Conf]
  45. Dennis Sylvester, Kurt Keutzer
    Getting to the bottom of deep submicron. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:203-211 [Conf]
  46. Rajeev R. Rao, David Blaauw, Dennis Sylvester
    Soft error reduction in combinational logic using gate resizing and flipflop selection. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:502-509 [Conf]
  47. Sarvesh H. Kulkarni, Dennis Sylvester, David Blaauw
    A statistical framework for post-silicon tuning through body bias clustering. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:39-46 [Conf]
  48. Kaviraj Chopra, Bo Zhai, David Blaauw, Dennis Sylvester
    A new statistical max operation for propagating skewness in statistical timing analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:237-243 [Conf]
  49. Shidhartha Das, Kanak Agarwal, David Blaauw, Dennis Sylvester
    Optimal Inductance for On-chip RLC Interconnections. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:264-0 [Conf]
  50. Saumil Shah, Kanak Agarwal, Dennis Sylvester
    A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:138-143 [Conf]
  51. Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar
    Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:228-233 [Conf]
  52. Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif
    Power-aware global signaling strategies. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:604-607 [Conf]
  53. Himanshu Kaul, Dennis Sylvester, Mark Anders, Ram Krishnamurthy
    Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:194-199 [Conf]
  54. Sarvesh H. Kulkarni, Ashish Srivastava, Dennis Sylvester
    A new algorithm for improved VDD assignment in low power dual VDD systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:200-205 [Conf]
  55. Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif
    Approaches to run-time and standby mode leakage reduction in global buses. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:188-193 [Conf]
  56. Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester
    Statistical estimation of leakage current considering inter- and intra-die process variation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:84-89 [Conf]
  57. Ashish Srivastava, Robert Bai, David Blaauw, Dennis Sylvester
    Modeling and analysis of leakage power considering within-die process variations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:64-67 [Conf]
  58. Bo Zhai, Scott Hanson, David Blaauw, Dennis Sylvester
    Analysis and mitigation of variability in subthreshold design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:20-25 [Conf]
  59. Scott Hanson, Dennis Sylvester, David Blaauw
    A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:338-341 [Conf]
  60. Harmander Deogun, Robert M. Senger, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka
    A dual-VDD boosted pulsed bus technique for low power and low leakage operation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:73-78 [Conf]
  61. Scott Hanson, Bo Zhai, David Blaauw, Dennis Sylvester, Andres Bryant, Xinlin Wang
    Energy optimality and variability in subthreshold design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:363-365 [Conf]
  62. Desmond Kirkpatrick, Pete Osler, Louis Scheffer, Prashant Saxena, Dennis Sylvester
    The great interconnect buffering debate: are you a chicken or an ostrich? [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:61- [Conf]
  63. Rajeev R. Rao, David Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif
    An efficient surface-based low-power buffer insertion algorithm. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:86-93 [Conf]
  64. Dennis Sylvester, Kurt Keutzer
    Getting to the bottom of deep submicron II: a global wiring paradigm. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:193-200 [Conf]
  65. Kanak Agarwal, Kevin J. Nowka, Harmander Deogun, Dennis Sylvester
    Power Gating with Multiple Sleep Modes. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:633-637 [Conf]
  66. Harmander Deogun, Rahul M. Rao, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka
    Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:88-93 [Conf]
  67. Harmander Deogun, Dennis Sylvester, David Blaauw
    Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:175-180 [Conf]
  68. Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang
    Performance Driven OPC for Mask Cost Reduction. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:270-275 [Conf]
  69. Vivek Joshi, Rajeev R. Rao, David Blaauw, Dennis Sylvester
    Logic SER Reduction through Flipflop Redesign. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:611-616 [Conf]
  70. Dongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester
    Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:287-292 [Conf]
  71. Himanshu Kaul, Dennis Sylvester
    Transition Aware Global Signaling (TAGS). [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:53-0 [Conf]
  72. Rahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown
    Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:284-290 [Conf]
  73. Jae-sun Seo, Prashant Singh, Dennis Sylvester, David Blaauw
    Self-Time Regenerators for High-Speed and Low-Power Interconnect. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:621-626 [Conf]
  74. Robert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David Blaauw
    An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:149-154 [Conf]
  75. Dennis Sylvester
    Measurement techniques and interconnect estimation. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:79-81 [Conf]
  76. Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester
    Investigation of performance metrics for interconnect stack architectures. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:23-29 [Conf]
  77. Kanak Agarwal, Dennis Sylvester, David Blaauw
    A library compatible driving point model for on-chip RLC interconnects. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:63-69 [Conf]
  78. Himanshu Kaul, Dennis Sylvester, David Blaauw
    Active shielding of RLC global interconnects. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:98-104 [Conf]
  79. Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu
    Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:77-0 [Conf]
  80. Yu-Shiang Lin, Dennis Sylvester
    A New Asymmetric Skewed Buffer Design for Runtime Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:824-827 [Conf]
  81. Dennis Sylvester, Kurt Keutzer
    Rethinking Deep-Submicron Circuit Design. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1999, v:32, n:11, pp:25-33 [Journal]
  82. Rajeev R. Rao, David Blaauw, Dennis Sylvester, Anirudh Devgan
    Modeling and Analysis of Parametric Yield under Power and Performance Constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:376-385 [Journal]
  83. Dennis Sylvester, Himanshu Kaul
    Power-Driven Challenges in Nanometer Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:6, pp:12-22 [Journal]
  84. Kanak Agarwal, Mridul Agarwal, Dennis Sylvester, David Blaauw
    Statistical interconnect metrics for physical-design optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1273-1288 [Journal]
  85. Kanak Agarwal, Dennis Sylvester, David Blaauw
    A library compatible driver output model for on-chip RLC transmission lines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:128-136 [Journal]
  86. Kanak Agarwal, Dennis Sylvester, David Blaauw
    A simple metric for slew rate of RC circuits based on two circuit moments. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1346-1354 [Journal]
  87. Kanak Agarwal, Dennis Sylvester, David Blaauw
    Modeling and analysis of crosstalk noise in coupled RLC interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:892-901 [Journal]
  88. Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester
    Gate-length biasing for runtime-leakage control. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1475-1485 [Journal]
  89. Dongwoo Lee, David Blaauw, Dennis Sylvester
    Static leakage reduction through simultaneous V/sub t//T/sub ox/ and state assignment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1014-1029 [Journal]
  90. Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester
    Analytical yield prediction considering leakage/performance correlation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1685-1695 [Journal]
  91. Takashi Sato, Yu Cao, Kanak Agarwal, Dennis Sylvester, Chenming Hu
    Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:560-572 [Journal]
  92. Ashish Srivastava, Dennis Sylvester
    Minimizing total power by simultaneous V/sub dd//V/sub th/ assignment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:665-677 [Journal]
  93. Dennis Sylvester, Kurt Keutzer
    A global wiring paradigm for deep submicron design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:242-252 [Journal]
  94. Yu Cao, Xuejue Huang, Dennis Sylvester, Tsu-Jae King, Chenming Hu
    Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:158-162 [Journal]
  95. Yu Cao, Xiao-Dong Yang, Xuejue Huang, Dennis Sylvester
    Switch-factor based loop RLC modeling for efficient timing analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:9, pp:1072-1078 [Journal]
  96. Himanshu Kaul, Dennis Sylvester
    Low-power on-chip communication based on transition-aware global signaling (TAGS). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:5, pp:464-476 [Journal]
  97. Himanshu Kaul, Dennis Sylvester, Mark Anders, Ram Krishnamurthy
    Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1225-1238 [Journal]
  98. Sarvesh H. Kulkarni, Dennis Sylvester
    High performance level conversion for dual VDD design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:9, pp:926-936 [Journal]
  99. Dongwoo Lee, David Blaauw, Dennis Sylvester
    Gate oxide leakage current analysis and reduction for VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:2, pp:155-166 [Journal]
  100. Rajeev R. Rao, Harmander Deogun, David Blaauw, Dennis Sylvester
    Bus encoding for total power reduction using a leakage-aware buffer configuration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:12, pp:1376-1383 [Journal]
  101. Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester
    Statistical analysis of subthreshold leakage current for VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:2, pp:131-139 [Journal]
  102. Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar
    Gate oxide leakage and delay tradeoffs for dual-T/sub ox/ circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:12, pp:1362-1375 [Journal]
  103. Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner
    The limit of dynamic voltage scaling and insomniac dynamic voltage scaling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1239-1252 [Journal]
  104. Dongwoo Lee, David Blaauw, Dennis Sylvester
    Runtime Leakage Minimization Through Probability-Aware Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:10, pp:1075-1088 [Journal]
  105. Scott Hanson, Mingoo Seok, Dennis Sylvester, David Blaauw
    Nanometer Device Scaling in Subthreshold Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:700-705 [Conf]
  106. Mingoo Seok, Scott Hanson, Dennis Sylvester, David Blaauw
    Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:694-699 [Conf]
  107. Ravikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer
    Top-k Aggressors Sets in Delay Noise Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:174-179 [Conf]
  108. Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester
    Line-End Shortening is Not Always a Failure. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:270-271 [Conf]
  109. Harmander Deogun, Dennis Sylvester, Kevin J. Nowka
    Fine grained multi-threshold CMOS for enhanced leakage reduction. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  110. Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin
    DVS for On-Chip Bus Designs Based on Timing Error Correction [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  111. Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylvester, Trevor N. Mudge
    Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  112. H. Singh, Kanak Agarwal, Dennis Sylvester, Kevin J. Nowka
    Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1215-1224 [Journal]
  113. Kanak Agarwal, Rahul M. Rao, Dennis Sylvester, Richard B. Brown
    Parametric Yield Analysis and Optimization in Leakage Dominated Technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:613-623 [Journal]
  114. Yu Cao, Xuejue Huang, N. H. Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Dennis Sylvester, Chenming Hu
    Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:799-805 [Journal]
  115. Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester
    Improved a priori interconnect predictions and technology extrapolation in the GTX system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:3-14 [Journal]
  116. Sarvesh H. Kulkarni, Dennis Sylvester
    Power Distribution Techniques for Dual VDD Circuits. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:2, pp:217-229 [Journal]

  117. An Energy Efficient Parallel Architecture Using Near Threshold Operation. [Citation Graph (, )][DBLP]


  118. Runtime leakage power estimation technique for combinational circuits. [Citation Graph (, )][DBLP]


  119. Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion. [Citation Graph (, )][DBLP]


  120. Investigation of diffusion rounding for post-lithography analysis. [Citation Graph (, )][DBLP]


  121. Clock tree synthesis with data-path sensitivity matching. [Citation Graph (, )][DBLP]


  122. Modeling crosstalk in statistical static timing analysis. [Citation Graph (, )][DBLP]


  123. Leakage power reduction using stress-enhanced layouts. [Citation Graph (, )][DBLP]


  124. Efficient Monte Carlo based incremental statistical timing analysis. [Citation Graph (, )][DBLP]


  125. Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence. [Citation Graph (, )][DBLP]


  126. Vicis: a reliable network for unreliable silicon. [Citation Graph (, )][DBLP]


  127. Closed-form modeling of layout-dependent mechanical stress. [Citation Graph (, )][DBLP]


  128. Efficient smart monte carlo based SSTA on graphics processing units with improved resource utilization. [Citation Graph (, )][DBLP]


  129. A highly resilient routing algorithm for fault-tolerant NoCs. [Citation Graph (, )][DBLP]


  130. A black box method for stability analysis of arbitrary SRAM cell structures. [Citation Graph (, )][DBLP]


  131. Process variation and temperature-aware reliability management. [Citation Graph (, )][DBLP]


  132. Yield-driven near-threshold SRAM design. [Citation Graph (, )][DBLP]


  133. Victim alignment in crosstalk aware timing analysis. [Citation Graph (, )][DBLP]


  134. On the decreasing significance of large standard cells in technology mapping. [Citation Graph (, )][DBLP]


  135. Soft-edge flip-flops for improved timing yield: design and optimization. [Citation Graph (, )][DBLP]


  136. A statistical approach for full-chip gate-oxide reliability analysis. [Citation Graph (, )][DBLP]


  137. STEEL: a technique for stress-enhanced standard cell library design. [Citation Graph (, )][DBLP]


  138. Post-fabrication measurement-driven oxide breakdown reliability prediction and management. [Citation Graph (, )][DBLP]


  139. Timing error correction techniques for voltage-scalable on-chip memories. [Citation Graph (, )][DBLP]


  140. A robust alternate repeater technique for high performance busses in the multi-core era. [Citation Graph (, )][DBLP]


  141. Low-voltage circuit design for widespread sensing applications. [Citation Graph (, )][DBLP]


  142. A robust edge encoding technique for energy-efficient multi-cycle interconnect. [Citation Graph (, )][DBLP]


  143. Optimal technology selection for minimizing energy and variability in low voltage applications. [Citation Graph (, )][DBLP]


  144. Energy efficient near-threshold chip multi-processing. [Citation Graph (, )][DBLP]


  145. Variation-aware gate sizing and clustering for post-silicon optimized circuits. [Citation Graph (, )][DBLP]


  146. Clock network design for ultra-low power applications. [Citation Graph (, )][DBLP]


  147. Low power circuit design based on heterojunction tunneling transistors (HETTs). [Citation Graph (, )][DBLP]


  148. Stress aware layout optimization. [Citation Graph (, )][DBLP]


  149. Fast and Accurate Waveform Analysis with Current Source Models. [Citation Graph (, )][DBLP]


  150. Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device Failures. [Citation Graph (, )][DBLP]


  151. Simultaneous extraction of effective gate length and low-field mobility in non-uniform devices. [Citation Graph (, )][DBLP]


  152. Reconfigurable energy efficient near threshold cache architectures. [Citation Graph (, )][DBLP]


  153. Reconfigurable Multicore Server Processors for Low Power Operation. [Citation Graph (, )][DBLP]


  154. ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon. [Citation Graph (, )][DBLP]


  155. Sensor-Driven Reliability and Wearout Management. [Citation Graph (, )][DBLP]


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