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## Search the dblp DataBase
David Blaauw:
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## Publications of Author- Mridul Agarwal, Kanak Agarwal, Dennis Sylvester, David Blaauw
**Statistical modeling of cross-coupling effects in VLSI interconnects.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:503-506 [Conf] - Kanak Agarwal, Dennis Sylvester, David Blaauw
**A simplified transmission-line based crosstalk noise model for on-chip RLC wiring.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2004, pp:858-864 [Conf] - Kanak Agarwal, Dennis Sylvester, David Blaauw, Anirudh Devgan
**Achieving continuous V**[Citation Graph (0, 0)][DBLP]_{T}performance in a dual V_{T}process. ASP-DAC, 2005, pp:393-398 [Conf] - Todd M. Austin, Valeria Bertacco, David Blaauw, Trevor N. Mudge
**Opportunities and challenges for better than worst-case design.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:2-7 [Conf] - David Blaauw, Anirudh Devgan, Farid N. Najm
**Leakage power: trends, analysis and avoidance.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:- [Conf] - Dongwoo Lee, David Blaauw, Dennis Sylvester
**Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:399-404 [Conf] - Leyla Nazhandali, Michael Minuth, Bo Zhai, Javin Olson, Todd M. Austin, David Blaauw
**A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution.**[Citation Graph (0, 0)][DBLP] CASES, 2005, pp:249-256 [Conf] - Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula
**Computation and Refinement of Statistical Bounds on Circuit Delay.**[Citation Graph (0, 0)][DBLP] DAC, 2003, pp:348-353 [Conf] - Aseem Agarwal, Kaviraj Chopra, David Blaauw, Vladimir Zolotov
**Circuit optimization using statistical static timing analysis.**[Citation Graph (0, 0)][DBLP] DAC, 2005, pp:321-324 [Conf] - Aseem Agarwal, Florentin Dartu, David Blaauw
**Statistical gate delay model considering multiple input switching.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:658-663 [Conf] - Kanak Agarwal, Dennis Sylvester, David Blaauw
**An effective capacitance based driver output model for on-chip RLC interconnects.**[Citation Graph (0, 0)][DBLP] DAC, 2003, pp:376-381 [Conf] - Kanak Agarwal, Dennis Sylvester, David Blaauw
**Simple metrics for slew rate of RC circuits based on two circuit moments.**[Citation Graph (0, 0)][DBLP] DAC, 2003, pp:950-953 [Conf] - Kanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula
**Variational delay metrics for interconnect timing analysis.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:381-384 [Conf] - Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
**Post-route gate sizing for crosstalk noise reduction.**[Citation Graph (0, 0)][DBLP] DAC, 2003, pp:954-957 [Conf] - David Blaauw, Kaviraj Chopra
**CAD tools for variation tolerance.**[Citation Graph (0, 0)][DBLP] DAC, 2005, pp:766- [Conf] - David Blaauw, Rajendran Panda, Abhijit Das
**Removing user specified false paths from timing graphs.**[Citation Graph (0, 0)][DBLP] DAC, 2000, pp:270-273 [Conf] - David Blaauw, Daniel G. Saab, Robert B. Mueller-Thuns, Jacob A. Abraham, Joseph T. Rahmeh
**Automatic Generation of Behavioral Models from Switch-Level Descriptions.**[Citation Graph (0, 0)][DBLP] DAC, 1989, pp:179-184 [Conf] - Rajat Chaudhry, David Blaauw, Rajendran Panda, Tim Edwards
**Current signature compression for IR-drop analysis.**[Citation Graph (0, 0)][DBLP] DAC, 2000, pp:162-167 [Conf] - Harmander Deogun, Rajeev R. Rao, Dennis Sylvester, David Blaauw
**Leakage-and crosstalk-aware bus encoding for total power reduction.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:779-782 [Conf] - Abhijit Dharchoudhury, Rajendran Panda, David Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden
**Design and Analysis of Power Distribution Networks in PowerPC Microprocessors.**[Citation Graph (0, 0)][DBLP] DAC, 1998, pp:738-743 [Conf] - Kaushik Gala, David Blaauw, Junfeng Wang, Vladimir Zolotov, Min Zhao
**Inductance 101: Analysis and Design Issues.**[Citation Graph (0, 0)][DBLP] DAC, 2001, pp:329-334 [Conf] - Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David Blaauw
**On-chip inductance modeling and analysis.**[Citation Graph (0, 0)][DBLP] DAC, 2000, pp:63-68 [Conf] - Eric Karl, David Blaauw, Dennis Sylvester, Trevor N. Mudge
**Reliability modeling and management in dynamic microprocessor-based systems.**[Citation Graph (0, 0)][DBLP] DAC, 2006, pp:1057-1060 [Conf] - Dongwoo Lee, David Blaauw
**Static leakage reduction through simultaneous threshold voltage and state assignment.**[Citation Graph (0, 0)][DBLP] DAC, 2003, pp:191-194 [Conf] - Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David Blaauw, Trevor N. Mudge
**Circuit-aware architectural simulation.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:305-310 [Conf] - Dongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester
**Analysis and minimization techniques for total leakage considering gate oxide leakage.**[Citation Graph (0, 0)][DBLP] DAC, 2003, pp:175-180 [Conf] - Dongwoo Lee, Vladimir Zolotov, David Blaauw
**Static timing analysis using backward signal propagation.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:664-669 [Conf] - Rafi Levy, David Blaauw, Gabi Braca, Aurobindo Dasgupta, Amir Grinshpon, Chanhee Oh, Boaz Orshav, Supamas Sirichotiyakul, Vladimir Zolotov
**ClariNet: a noise analysis tool for deep submicron design.**[Citation Graph (0, 0)][DBLP] DAC, 2000, pp:233-238 [Conf] - Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David Blaauw
**Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization.**[Citation Graph (0, 0)][DBLP] DAC, 1998, pp:388-391 [Conf] - Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
**A stochastic approach To power grid analysis.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:171-176 [Conf] - Jan M. Rabaey, Dennis Sylvester, David Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang
**Reshaping EDA for power.**[Citation Graph (0, 0)][DBLP] DAC, 2003, pp:15- [Conf] - Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester
**Parametric yield estimation considering leakage variability.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:442-447 [Conf] - Supamas Sirichotiyakul, David Blaauw, Chanhee Oh, Rafi Levy, Vladimir Zolotov, Jingyan Zuo
**Driver Modeling and Alignment for Worst-Case Delay Noise.**[Citation Graph (0, 0)][DBLP] DAC, 2001, pp:720-725 [Conf] - Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David Blaauw
**Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing.**[Citation Graph (0, 0)][DBLP] DAC, 1999, pp:436-441 [Conf] - Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David Blaauw, Stephen W. Director
**Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance.**[Citation Graph (0, 0)][DBLP] DAC, 2005, pp:535-540 [Conf] - Ashish Srivastava, Dennis Sylvester, David Blaauw
**Statistical optimization of leakage power considering process variations using dual-Vth and sizing.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:773-778 [Conf] - Ashish Srivastava, Dennis Sylvester, David Blaauw
**Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:783-787 [Conf] - Bhavana Thudi, David Blaauw
**Non-iterative switching window computation for delay-noise.**[Citation Graph (0, 0)][DBLP] DAC, 2003, pp:390-395 [Conf] - Sarma B. K. Vrudhula, David Blaauw, Supamas Sirichotiyakul
**Estimation of the likelihood of capacitive coupling noise.**[Citation Graph (0, 0)][DBLP] DAC, 2002, pp:653-658 [Conf] - Bo Zhai, David Blaauw, Dennis Sylvester, Krisztián Flautner
**Theoretical and practical limits of dynamic voltage scaling.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:868-873 [Conf] - Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David Blaauw
**Hierarchical analysis of power distribution networks.**[Citation Graph (0, 0)][DBLP] DAC, 2000, pp:150-155 [Conf] - Murat R. Becer, Vladimir Zolotov, David Blaauw, Rajendran Panda, Ibrahim N. Hajj
**Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model .**[Citation Graph (0, 0)][DBLP] DATE, 2002, pp:456-464 [Conf] - Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula
**Statistical Timing Analysis Using Bounds.**[Citation Graph (0, 0)][DBLP] DATE, 2003, pp:10062-10067 [Conf] - Aseem Agarwal, Kaviraj Chopra, David Blaauw
**Statistical Timing Based Optimization using Gate Sizing.**[Citation Graph (0, 0)][DBLP] DATE, 2005, pp:400-405 [Conf] - Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin
**DVS for On-Chip Bus Designs Based on Timing Error Correction.**[Citation Graph (0, 0)][DBLP] DATE, 2005, pp:80-85 [Conf] - Dongwoo Lee, Harmander Deogun, David Blaauw, Dennis Sylvester
**Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization.**[Citation Graph (0, 0)][DBLP] DATE, 2004, pp:494-499 [Conf] - Rajeev R. Rao, Kaviraj Chopra, David Blaauw, Dennis Sylvester
**An efficient static algorithm for computing the soft error rates of combinational circuits.**[Citation Graph (0, 0)][DBLP] DATE, 2006, pp:164-169 [Conf] - Ashish Srivastava, Dennis Sylvester, David Blaauw
**Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design.**[Citation Graph (0, 0)][DBLP] DATE, 2004, pp:718-719 [Conf] - David Blaauw, Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Junfeng Wang
**On-chip inductance modeling.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2000, pp:75-80 [Conf] - Amit Jain, David Blaauw
**Slack borrowing in flip-flop based sequential circuits.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2005, pp:96-101 [Conf] - Himanshu Kaul, Dennis Sylvester, David Blaauw
**Active shields: a new approach to shielding global wires.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2002, pp:112-117 [Conf] - David Blaauw, Robert B. Mueller-Thuns, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham
**SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction.**[Citation Graph (0, 0)][DBLP] ICCAD, 1990, pp:66-69 [Conf] - David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda
**Slope Propagation in Static Timing Analysis.**[Citation Graph (0, 0)][DBLP] ICCAD, 2000, pp:338-343 [Conf] - Aseem Agarwal, David Blaauw, Vladimir Zolotov
**Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations.**[Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:900-907 [Conf] - Aseem Agarwal, David Blaauw, Vladimir Zolotov
**Statistical Clock Skew Analysis Considering Intra-Die Process Variations.**[Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:914-921 [Conf] - Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw
**Estimation of signal arrival times in the presence of delay noise.**[Citation Graph (0, 0)][DBLP] ICCAD, 2002, pp:418-422 [Conf] - Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw
**AU: Timing Analysis Under Uncertainty.**[Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:615-620 [Conf] - Kaviraj Chopra, Saumil Shah, Ashish Srivastava, David Blaauw, Dennis Sylvester
**Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation.**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:1023-1028 [Conf] - Li Ding 0002, David Blaauw, Pinaki Mazumder
**Efficient crosstalk noise modeling using aggressor and tree reductions.**[Citation Graph (0, 0)][DBLP] ICCAD, 2002, pp:595-600 [Conf] - Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, G. Vijayan, David Blaauw
**Library-less synthesis for static CMOS combinational logic circuits.**[Citation Graph (0, 0)][DBLP] ICCAD, 1997, pp:658-662 [Conf] - Alexey Glebov, Sergey Gavrilov, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov
**False-Noise Analysis using Logic Implications.**[Citation Graph (0, 0)][DBLP] ICCAD, 2001, pp:515-0 [Conf] - Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
**A precorrected-FFT method for simulating on-chip inductance.**[Citation Graph (0, 0)][DBLP] ICCAD, 2002, pp:221-227 [Conf] - Amit Jain, David Blaauw, Vladimir Zolotov
**Accurate delay computation for noisy waveform shapes.**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:947-953 [Conf] - Nam Sung Kim, David Blaauw, Trevor N. Mudge
**Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches.**[Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:627-632 [Conf] - Steven M. Martin, Krisztián Flautner, Trevor N. Mudge, David Blaauw
**Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads.**[Citation Graph (0, 0)][DBLP] ICCAD, 2002, pp:721-725 [Conf] - D. Nadezhin, Sergey Gavrilov, Alexey Glebov, Y. Egorov, Vladimir Zolotov, David Blaauw, Rajendran Panda, Murat R. Becer, A. Ardelea, A. Patel
**SOI Transistor Model for Fast Transient Simulation.**[Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:120128- [Conf] - Sanjay Pant, David Blaauw
**Static timing analysis considering power supply variations.**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:365-371 [Conf] - Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
**Vectorless Analysis of Supply Noise Induced Delay Variation.**[Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:184-192 [Conf] - Saumil Shah, Ashish Srivastava, Dushyant Sharma, Dennis Sylvester, David Blaauw, Vladimir Zolotov
**Discrete Vt assignment and gate sizing using a self-snapping continuous formulation.**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:705-712 [Conf] - Vladimir Zolotov, David Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy
**Noise propagation and failure criteria for VLSI designs.**[Citation Graph (0, 0)][DBLP] ICCAD, 2002, pp:587-594 [Conf] - Rajeev R. Rao, David Blaauw, Dennis Sylvester
**Soft error reduction in combinational logic using gate resizing and flipflop selection.**[Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:502-509 [Conf] - Sarvesh H. Kulkarni, Dennis Sylvester, David Blaauw
**A statistical framework for post-silicon tuning through body bias clustering.**[Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:39-46 [Conf] - Brian Cline, Kaviraj Chopra, David Blaauw, Yu Cao
**Analysis and modeling of CD variation for statistical static timing.**[Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:60-66 [Conf] - Kaviraj Chopra, Bo Zhai, David Blaauw, Dennis Sylvester
**A new statistical max operation for propagating skewness in statistical timing analysis.**[Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:237-243 [Conf] - Shidhartha Das, Kanak Agarwal, David Blaauw, Dennis Sylvester
**Optimal Inductance for On-chip RLC Interconnections.**[Citation Graph (0, 0)][DBLP] ICCD, 2003, pp:264-0 [Conf] - Abhijit Dharchoudhury, David Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning
**Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor.**[Citation Graph (0, 0)][DBLP] ICCD, 1997, pp:143-148 [Conf] - Krisztián Flautner, Nam Sung Kim, Steve Martin, David Blaauw, Trevor N. Mudge
**Drowsy Caches: Simple Techniques for Reducing Leakage Power.**[Citation Graph (0, 0)][DBLP] ISCA, 2002, pp:148-157 [Conf] - Leyla Nazhandali, Bo Zhai, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, Todd M. Austin, David Blaauw
**Energy Optimization of Subthreshold-Voltage Sensor Network Processors.**[Citation Graph (0, 0)][DBLP] ISCA, 2005, pp:197-207 [Conf] - Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
**Table look-up based compact modeling for on-chip interconnect timing and noise analysis.**[Citation Graph (0, 0)][DBLP] ISCAS (4), 2003, pp:668-671 [Conf] - Li Ding 0002, Pinaki Mazumder, David Blaauw
**Crosstalk noise estimation using effective coupling capacitance.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2002, pp:645-648 [Conf] - David Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards
**Emerging power management tools for processor design.**[Citation Graph (0, 0)][DBLP] ISLPED, 1998, pp:143-148 [Conf] - Alexey Glebov, David Blaauw, Larry G. Jones
**Transistor reordering for low power CMOS gates using an SP-BDD representation.**[Citation Graph (0, 0)][DBLP] ISLPD, 1995, pp:161-166 [Conf] - Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David Blaauw, Trevor N. Mudge
**Reducing pipeline energy demands with local DVS and dynamic retiming.**[Citation Graph (0, 0)][DBLP] ISLPED, 2004, pp:319-324 [Conf] - Rajendran Panda, David Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju
**Model and analysis for combined package and on-chip power grid simulation.**[Citation Graph (0, 0)][DBLP] ISLPED, 2000, pp:179-184 [Conf] - Rajendran Panda, Savithri Sundareswaran, David Blaauw
**On the interaction of power distribution network with substrate.**[Citation Graph (0, 0)][DBLP] ISLPED, 2001, pp:388-393 [Conf] - Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester
**Statistical estimation of leakage current considering inter- and intra-die process variation.**[Citation Graph (0, 0)][DBLP] ISLPED, 2003, pp:84-89 [Conf] - Ashish Srivastava, Robert Bai, David Blaauw, Dennis Sylvester
**Modeling and analysis of leakage power considering within-die process variations.**[Citation Graph (0, 0)][DBLP] ISLPED, 2002, pp:64-67 [Conf] - Bo Zhai, Scott Hanson, David Blaauw, Dennis Sylvester
**Analysis and mitigation of variability in subthreshold design.**[Citation Graph (0, 0)][DBLP] ISLPED, 2005, pp:20-25 [Conf] - Scott Hanson, Dennis Sylvester, David Blaauw
**A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits.**[Citation Graph (0, 0)][DBLP] ISLPED, 2006, pp:338-341 [Conf] - Scott Hanson, Bo Zhai, David Blaauw, Dennis Sylvester, Andres Bryant, Xinlin Wang
**Energy optimality and variability in subthreshold design.**[Citation Graph (0, 0)][DBLP] ISLPED, 2006, pp:363-365 [Conf] - Rajeev R. Rao, David Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif
**An efficient surface-based low-power buffer insertion algorithm.**[Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:86-93 [Conf] - Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
**Post-Route Gate Sizing for Crosstalk Noise Reduction.**[Citation Graph (0, 0)][DBLP] ISQED, 2003, pp:171-176 [Conf] - David Blaauw, Rajendran Panda
**On-Chip Inductance Extraction and Modelin.**[Citation Graph (0, 0)][DBLP] ISQED, 2001, pp:14- [Conf] - Murat R. Becer, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj
**A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance.**[Citation Graph (0, 0)][DBLP] ISQED, 2001, pp:158-0 [Conf] - Murat R. Becer, Rajendran Panda, David Blaauw, Ibrahim N. Hajj
**Pre-route Noise Estimation in Deep Submicron Integrated Circuits.**[Citation Graph (0, 0)][DBLP] ISQED, 2002, pp:413-418 [Conf] - Harmander Deogun, Dennis Sylvester, David Blaauw
**Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate.**[Citation Graph (0, 0)][DBLP] ISQED, 2005, pp:175-180 [Conf] - Alexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov, Rajendran Panda, Chanhee Oh
**False-Noise Analysis Using Resolution Method.**[Citation Graph (0, 0)][DBLP] ISQED, 2002, pp:437-0 [Conf] - Vivek Joshi, Rajeev R. Rao, David Blaauw, Dennis Sylvester
**Logic SER Reduction through Flipflop Redesign.**[Citation Graph (0, 0)][DBLP] ISQED, 2006, pp:611-616 [Conf] - Dongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester
**Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design.**[Citation Graph (0, 0)][DBLP] ISQED, 2003, pp:287-292 [Conf] - Woo Hyung Lee, Sanjay Pant, David Blaauw
**Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids.**[Citation Graph (0, 0)][DBLP] ISQED, 2004, pp:131-136 [Conf] - Mini Nanua, David Blaauw, Chanhee Oh
**Leakage Current Modeling in PD SOI Circuits.**[Citation Graph (0, 0)][DBLP] ISQED, 2005, pp:113-117 [Conf] - Chanhee Oh, David Blaauw, Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Aurobindo Dasgupta
**Static Electromigration Analysis for Signal Interconnects.**[Citation Graph (0, 0)][DBLP] ISQED, 2003, pp:377-0 [Conf] - David Roberts, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner
**Error Analysis for the Support of Robust Voltage Scaling.**[Citation Graph (0, 0)][DBLP] ISQED, 2005, pp:65-70 [Conf] - Vladimir Zolotov, David Blaauw, Rajendran Panda, Chanhee Oh
**Noise Injection and Propagation in High Performance Designs.**[Citation Graph (0, 0)][DBLP] ISQED, 2002, pp:425-430 [Conf] - Jae-sun Seo, Prashant Singh, Dennis Sylvester, David Blaauw
**Self-Time Regenerators for High-Speed and Low-Power Interconnect.**[Citation Graph (0, 0)][DBLP] ISQED, 2007, pp:621-626 [Conf] - Mini Nanua, David Blaauw
**Investigating Crosstalk in Sub-Threshold Circuits.**[Citation Graph (0, 0)][DBLP] ISQED, 2007, pp:639-646 [Conf] - Robert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David Blaauw
**An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages.**[Citation Graph (0, 0)][DBLP] ISVLSI, 2003, pp:149-154 [Conf] - Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge
**Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation.**[Citation Graph (0, 0)][DBLP] MICRO, 2003, pp:7-18 [Conf] - Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge
**Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction.**[Citation Graph (0, 0)][DBLP] MICRO, 2002, pp:219-230 [Conf] - Fadi A. Aloul, Soha Hassoun, Karem A. Sakallah, David Blaauw
**Robust SAT-Based Search Algorithm for Leakage Power Reduction.**[Citation Graph (0, 0)][DBLP] PATMOS, 2002, pp:167-177 [Conf] - Mini Nanua, David Blaauw
**Receiver Modeling for Static Functional Crosstalk Analysis.**[Citation Graph (0, 0)][DBLP] PATMOS, 2006, pp:329-339 [Conf] - Murat R. Becer, David Blaauw, Ibrahim N. Hajj, Rajendran Panda
**Early probabilistic noise estimation for capacitively coupled interconnects.**[Citation Graph (0, 0)][DBLP] SLIP, 2002, pp:77-83 [Conf] - Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula
**Statistical timing analysis using bounds and selective enumeration.**[Citation Graph (0, 0)][DBLP] Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:16-21 [Conf] - Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula
**Statistical timing analysis using bounds and selective enumeration.**[Citation Graph (0, 0)][DBLP] Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:29-36 [Conf] - Kanak Agarwal, Dennis Sylvester, David Blaauw
**A library compatible driving point model for on-chip RLC interconnects.**[Citation Graph (0, 0)][DBLP] Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:63-69 [Conf] - Himanshu Kaul, Dennis Sylvester, David Blaauw
**Active shielding of RLC global interconnects.**[Citation Graph (0, 0)][DBLP] Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:98-104 [Conf] - Bhavana Thudi, David Blaauw
**Efficient switching window computation for cross-talk noise.**[Citation Graph (0, 0)][DBLP] Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:84-91 [Conf] - Rajat Chaudhry, Rajendran Panda, Tim Edwards, David Blaauw
**Design and Analysis of Power Distribution Networks with Accurate RLC Models.**[Citation Graph (0, 0)][DBLP] VLSI Design, 2000, pp:151-155 [Conf] - Savithri Sundareswaran, David Blaauw, Abhijit Dharchoudhury
**A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1999, pp:175-180 [Conf] - Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner
**Making Typical Silicon Matter with Razor.**[Citation Graph (0, 0)][DBLP] IEEE Computer, 2004, v:37, n:3, pp:57-65 [Journal] - Todd M. Austin, David Blaauw, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Wayne Wolf
**Mobile Supercomputers.**[Citation Graph (0, 0)][DBLP] IEEE Computer, 2004, v:37, n:5, pp:81-83 [Journal] - Nam Sung Kim, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner, Jie S. Hu, Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan
**Leakage Current: Moore's Law Meets Static Power.**[Citation Graph (0, 0)][DBLP] IEEE Computer, 2003, v:36, n:12, pp:68-75 [Journal] - David Blaauw, Luciano Lavagno
**Guest Editors' Introduction: Hot Topics at This Year's Design Automation Conference.**[Citation Graph (0, 0)][DBLP] IEEE Design & Test of Computers, 2002, v:19, n:4, pp:72-73 [Journal] - Rajendran Panda, Savithri Sundareswaran, David Blaauw
**Impact of Low-Impedance Substrate on Power Supply Integrity.**[Citation Graph (0, 0)][DBLP] IEEE Design & Test of Computers, 2003, v:20, n:3, pp:16-22 [Journal] - Rajeev R. Rao, David Blaauw, Dennis Sylvester, Anirudh Devgan
**Modeling and Analysis of Parametric Yield under Power and Performance Constraints.**[Citation Graph (0, 0)][DBLP] IEEE Design & Test of Computers, 2005, v:22, n:4, pp:376-385 [Journal] - David Blaauw, Steve Martin, Trevor N. Mudge, Krisztián Flautner
**Leakage Current Reduction in VLSI Systems.**[Citation Graph (0, 0)][DBLP] Journal of Circuits, Systems, and Computers, 2002, v:11, n:6, pp:621-636 [Journal] - Dan Ernst, Shidhartha Das, Seokwoo Lee, David Blaauw, Todd M. Austin, Trevor N. Mudge, Nam Sung Kim, Krisztián Flautner
**Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation.**[Citation Graph (0, 0)][DBLP] IEEE Micro, 2004, v:24, n:6, pp:10-20 [Journal] - Kanak Agarwal, Mridul Agarwal, Dennis Sylvester, David Blaauw
**Statistical interconnect metrics for physical-design optimization.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1273-1288 [Journal] - Kanak Agarwal, Dennis Sylvester, David Blaauw
**A library compatible driver output model for on-chip RLC transmission lines.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:128-136 [Journal] - Kanak Agarwal, Dennis Sylvester, David Blaauw
**A simple metric for slew rate of RC circuits based on two circuit moments.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1346-1354 [Journal] - Kanak Agarwal, Dennis Sylvester, David Blaauw
**Modeling and analysis of crosstalk noise in coupled RLC interconnects.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:892-901 [Journal] - Aseem Agarwal, Vladimir Zolotov, David Blaauw
**Statistical clock skew analysis considering intradie-process variations.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1231-1242 [Journal] - Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw
**Probability distribution of signal arrival times using Bayesian networks.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1784-1794 [Journal] - David Blaauw, Chanhee Oh, Vladimir Zolotov, Aurobindo Dasgupta
**Static electromigration analysis for on-chip signal interconnects.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:39-48 [Journal] - Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
**Postroute gate sizing for crosstalk noise reduction.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1670-1677 [Journal] - Larry G. Jones, David Blaauw
**A cache-based method for accelerating switch-level simulation.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:211-218 [Journal] - Dongwoo Lee, David Blaauw, Dennis Sylvester
**Static leakage reduction through simultaneous V/sub t//T/sub ox/ and state assignment.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1014-1029 [Journal] - Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester
**Analytical yield prediction considering leakage/performance correlation.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1685-1695 [Journal] - Alexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov
**False-noise analysis using logic implications.**[Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:3, pp:474-498 [Journal] - Nam Sung Kim, David Blaauw, Trevor N. Mudge
**Quantitative analysis and optimization techniques for on-chip cache leakage power.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2005, v:13, n:10, pp:1147-1156 [Journal] - Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge
**Circuit and microarchitectural techniques for reducing cache leakage power.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2004, v:12, n:2, pp:167-184 [Journal] - Dongwoo Lee, David Blaauw, Dennis Sylvester
**Gate oxide leakage current analysis and reduction for VLSI circuits.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2004, v:12, n:2, pp:155-166 [Journal] - Rajeev R. Rao, Harmander Deogun, David Blaauw, Dennis Sylvester
**Bus encoding for total power reduction using a leakage-aware buffer configuration.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2005, v:13, n:12, pp:1376-1383 [Journal] - Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester
**Statistical analysis of subthreshold leakage current for VLSI circuits.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2004, v:12, n:2, pp:131-139 [Journal] - Dongwoo Lee, David Blaauw, Dennis Sylvester
**Runtime Leakage Minimization Through Probability-Aware Optimization.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2006, v:14, n:10, pp:1075-1088 [Journal] - Scott Hanson, Mingoo Seok, Dennis Sylvester, David Blaauw
**Nanometer Device Scaling in Subthreshold Circuits.**[Citation Graph (0, 0)][DBLP] DAC, 2007, pp:700-705 [Conf] - Mingoo Seok, Scott Hanson, Dennis Sylvester, David Blaauw
**Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design.**[Citation Graph (0, 0)][DBLP] DAC, 2007, pp:694-699 [Conf] - Ravikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer
**Top-k Aggressors Sets in Delay Noise Analysis.**[Citation Graph (0, 0)][DBLP] DAC, 2007, pp:174-179 [Conf] - David Blaauw, Bo Zhai
**Energy efficient design for subthreshold supply voltage operation.**[Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf] - Mini Nanua, David Blaauw
**Crosstalk Waveform Modeling Using Wave Fitting.**[Citation Graph (0, 0)][DBLP] PATMOS, 2007, pp:211-221 [Conf] - Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin
**DVS for On-Chip Bus Designs Based on Timing Error Correction**[Citation Graph (0, 0)][DBLP] CoRR, 2007, v:0, n:, pp:- [Journal] - Aseem Agarwal, Kaviraj Chopra, David Blaauw
**Statistical Timing Based Optimization using Gate Sizing**[Citation Graph (0, 0)][DBLP] CoRR, 2007, v:0, n:, pp:- [Journal] - Kaushik Gala, David Blaauw, Vladimir Zolotov, P. M. Vaidya, A. Joshi
**Inductance model and analysis methodology for high-speed on-chip interconnect.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:730-745 [Journal] - Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Rajendran Panda, David Blaauw
**Duet: an accurate leakage estimation and optimization tool for dual-V**[Citation Graph (0, 0)][DBLP]_{t}circuits. IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:79-90 [Journal] - David Blaauw, Supamas Sirichotiyakul, Chanhee Oh
**Driver modeling and alignment for worst-case delay noise.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:157-166 [Journal] **An Energy Efficient Parallel Architecture Using Near Threshold Operation.**[Citation Graph (, )][DBLP]**Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks.**[Citation Graph (, )][DBLP]**Modeling crosstalk in statistical static timing analysis.**[Citation Graph (, )][DBLP]**Leakage power reduction using stress-enhanced layouts.**[Citation Graph (, )][DBLP]**Efficient Monte Carlo based incremental statistical timing analysis.**[Citation Graph (, )][DBLP]**Addressing design margins through error-tolerant circuits.**[Citation Graph (, )][DBLP]**Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence.**[Citation Graph (, )][DBLP]**Vicis: a reliable network for unreliable silicon.**[Citation Graph (, )][DBLP]**Worst-case aggressor-victim alignment with current-source driver models.**[Citation Graph (, )][DBLP]**Closed-form modeling of layout-dependent mechanical stress.**[Citation Graph (, )][DBLP]**Efficient smart monte carlo based SSTA on graphics processing units with improved resource utilization.**[Citation Graph (, )][DBLP]**Transistor-Specific Delay Modeling for SSTA.**[Citation Graph (, )][DBLP]**Fast power loss calculation for digital static CMOS circuits.**[Citation Graph (, )][DBLP]**A highly resilient routing algorithm for fault-tolerant NoCs.**[Citation Graph (, )][DBLP]**A black box method for stability analysis of arbitrary SRAM cell structures.**[Citation Graph (, )][DBLP]**Process variation and temperature-aware reliability management.**[Citation Graph (, )][DBLP]**Yield-driven near-threshold SRAM design.**[Citation Graph (, )][DBLP]**Victim alignment in crosstalk aware timing analysis.**[Citation Graph (, )][DBLP]**On the decreasing significance of large standard cells in technology mapping.**[Citation Graph (, )][DBLP]**Soft-edge flip-flops for improved timing yield: design and optimization.**[Citation Graph (, )][DBLP]**A statistical approach for full-chip gate-oxide reliability analysis.**[Citation Graph (, )][DBLP]**STEEL: a technique for stress-enhanced standard cell library design.**[Citation Graph (, )][DBLP]**Post-fabrication measurement-driven oxide breakdown reliability prediction and management.**[Citation Graph (, )][DBLP]**An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks.**[Citation Graph (, )][DBLP]**Timing error correction techniques for voltage-scalable on-chip memories.**[Citation Graph (, )][DBLP]**Low-voltage circuit design for widespread sensing applications.**[Citation Graph (, )][DBLP]**A robust edge encoding technique for energy-efficient multi-cycle interconnect.**[Citation Graph (, )][DBLP]**Optimal technology selection for minimizing energy and variability in low voltage applications.**[Citation Graph (, )][DBLP]**Energy efficient near-threshold chip multi-processing.**[Citation Graph (, )][DBLP]**Variation-aware gate sizing and clustering for post-silicon optimized circuits.**[Citation Graph (, )][DBLP]**Clock network design for ultra-low power applications.**[Citation Graph (, )][DBLP]**Low power circuit design based on heterojunction tunneling transistors (HETTs).**[Citation Graph (, )][DBLP]**Stress aware layout optimization.**[Citation Graph (, )][DBLP]**Fast and Accurate Waveform Analysis with Current Source Models.**[Citation Graph (, )][DBLP]**Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device Failures.**[Citation Graph (, )][DBLP]**Reconfigurable energy efficient near threshold cache architectures.**[Citation Graph (, )][DBLP]**Reconfigurable Multicore Server Processors for Low Power Operation.**[Citation Graph (, )][DBLP]**Power Grid Physics and Implications for CAD.**[Citation Graph (, )][DBLP]**ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon.**[Citation Graph (, )][DBLP]**Sensor-Driven Reliability and Wearout Management.**[Citation Graph (, )][DBLP]
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