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Chenming Hu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu
    Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:77-86 [Conf]
  2. Kaustav Banerjee, Amit Mehrotra, Alberto L. Sangiovanni-Vincentelli, Chenming Hu
    On Thermal Effects in Deep Sub-Micron VLSI Interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:885-891 [Conf]
  3. Michael Orshansky, James C. Chen, Chenming Hu
    A Statistical Performance Simulation Methodology for VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:402-407 [Conf]
  4. Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester
    Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:56-61 [Conf]
  5. Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu
    Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:62-67 [Conf]
  6. Kai Chen 0002, Chenming Hu
    Device and technology optimizations for low power design in deep sub-micron regime. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:312-316 [Conf]
  7. Kai Chen 0002, Yuhua Cheng, Chenming Hu
    Device design for low power electronics with accurate deep submicrometer LDD-MOSFET models. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:197-200 [Conf]
  8. Yu Cao, Xuejue Huang, Chenming Hu, Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie
    Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:185-190 [Conf]
  9. Jin He, Xuemei Xi, Mansun Chan, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu
    A Non-Charge-Sheet Based Analytical Model of Undoped Symmetric Double-Gate MOSFETs Using SPP Approach. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:45-50 [Conf]
  10. Jin He, Jane Xi, Mansun Chan, Hui Wan, Mohan V. Dunga, Babak Heydari, Ali M. Niknejad, Chenming Hu
    Charge-Based Core and the Model Architecture of BSIM5. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:96-101 [Conf]
  11. Pin Su, Samel K. H. Fung, Weidong Liu, Chenming Hu
    Studying the Impact of Gate Tunneling on Dynamic Behaviors of Partially-Depleted SOI CMOS Using BSIMPD. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:487-491 [Conf]
  12. Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu
    Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:77-0 [Conf]
  13. Yuhua Cheng, Kai Chen 0002, Kiyotaka Imai, Chenming Hu
    A unified MOSFET channel charge model for device modeling in circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:8, pp:641-644 [Journal]
  14. Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu
    Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:544-553 [Journal]
  15. Hong June Park, Ping Keung Ko, Chenming Hu
    A charge sheet capacitance model of short channel MOSFETs for SPICE. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:376-389 [Journal]
  16. Hong June Park, Ping Keung Ko, Chenming Hu
    A charge conserving non-quasi-state (NQS) MOSFET model for SPICE transient analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:629-642 [Journal]
  17. Hong June Park, Ping Keung Ko, Chenming Hu
    A non-quasi-static MOSFET model for SPICE-AC analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:10, pp:1247-1257 [Journal]
  18. Takashi Sato, Yu Cao, Kanak Agarwal, Dennis Sylvester, Chenming Hu
    Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:560-572 [Journal]
  19. Robert H. Tu, Elyse Rosenbaum, Wilson Y. Chan, Chester C. Li, Eric Minami, Khandker Quader, Ping K. Ko, Chenming Hu
    Berkeley reliability tools-BERT. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1524-1534 [Journal]
  20. Yu Cao, Xuejue Huang, Dennis Sylvester, Tsu-Jae King, Chenming Hu
    Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:158-162 [Journal]
  21. Mansun Chan, Xuemei Xi, Jin He, Kanyu M. Cao, Mohan V. Dunga, Ali M. Niknejad, Ping K. Ko, Chenming Hu
    Practical compact modeling approaches and options for sub-0.1 mum CMOS technologies. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:3, pp:399-404 [Journal]
  22. Yu Cao, Xuejue Huang, N. H. Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Dennis Sylvester, Chenming Hu
    Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:799-805 [Journal]
  23. Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester
    Improved a priori interconnect predictions and technology extrapolation in the GTX system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:3-14 [Journal]

  24. Compact Modeling of Variation in FinFET SRAM Cells. [Citation Graph (, )][DBLP]


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