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Vineet Agarwal:
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- Vineet Agarwal, Navneeth Kankani, Ravishankar Rao, Sarvesh Bhardwaj, Janet Wang
An efficient combinationality check technique for the synthesis of cyclic combinational circuits. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:212-215 [Conf]
- Vineet Agarwal, Janet Meiling Wang
Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA). [Citation Graph (0, 0)][DBLP] ASP-DAC, 2006, pp:718-723 [Conf]
- Navneeth Kankani, Vineet Agarwal, Janet Meiling Wang
A probabilistic analysis of pipelined global interconnect under process variations. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2006, pp:724-729 [Conf]
Delay Uncertainty Reduction by Interconnect and Gate Splitting. [Citation Graph (, )][DBLP]
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