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Ravishankar Rao:
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Publications of Author
- Vineet Agarwal, Navneeth Kankani, Ravishankar Rao, Sarvesh Bhardwaj, Janet Wang
An efficient combinationality check technique for the synthesis of cyclic combinational circuits. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:212-215 [Conf]
- Ravishankar Rao, Sarma B. K. Vrudhula, Musaravakkam S. Krishnan
Disk drive energy optimization for audio-video applications. [Citation Graph (0, 0)][DBLP] CASES, 2004, pp:93-103 [Conf]
- John Oliver, Ravishankar Rao, Michael Brown, Jennifer Mankin, Diana Franklin, Frederic T. Chong, Venkatesh Akella
Tile size selection for low-power tile-based architectures. [Citation Graph (0, 0)][DBLP] Conf. Computing Frontiers, 2006, pp:83-94 [Conf]
- Ravishankar Rao, Sarma B. K. Vrudhula
Energy optimal speed control of devices with discrete speed sets. [Citation Graph (0, 0)][DBLP] DAC, 2005, pp:901-904 [Conf]
- Ravishankar Rao, Mark Oskin, Frederic T. Chong
HLSpower: Hybrid Statistical Modeling of the Superscalar Power-Performance Design Space. [Citation Graph (0, 0)][DBLP] HiPC, 2002, pp:620-629 [Conf]
- Ravishankar Rao, Justin Wenck, Diana Franklin, Rajeevan Amirtharajah, Venkatesh Akella
Segmented Bitline Cache: Exploiting Non-uniform Memory Access Patterns. [Citation Graph (0, 0)][DBLP] HiPC, 2006, pp:123-134 [Conf]
- Ravishankar Rao, Sarma B. K. Vrudhula
Energy optimization for a two-device data flow chain. [Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:268-274 [Conf]
- Ravishankar Rao, Sarma B. K. Vrudhula
Battery optimization vs energy optimization: which to choose and when? [Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:439-445 [Conf]
- John Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Franklin, Venkatesh Akella, Frederic T. Chong
Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor. [Citation Graph (0, 0)][DBLP] ISCA, 2004, pp:150-161 [Conf]
- Ravishankar Rao, Sarma B. K. Vrudhula, Daler N. Rakhmatov
Analysis of discharge techniques for multiple battery systems. [Citation Graph (0, 0)][DBLP] ISLPED, 2003, pp:44-47 [Conf]
- Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Chakrabarti, Naehyuck Chang
An optimal analytical solution for processor speed control with thermal constraints. [Citation Graph (0, 0)][DBLP] ISLPED, 2006, pp:292-297 [Conf]
- John Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Dean Copsey, Diana Keen, Venkatesh Akella, Frederic T. Chong
Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture. [Citation Graph (0, 0)][DBLP] PACS, 2003, pp:73-85 [Conf]
- Ravishankar Rao, Sarma B. K. Vrudhula, Daler N. Rakhmatov
Battery Modeling for Energy-Aware System Design. [Citation Graph (0, 0)][DBLP] IEEE Computer, 2003, v:36, n:12, pp:77-87 [Journal]
- Ravishankar Rao, Sarma B. K. Vrudhula
Performance optimal processor throttling under thermal constraints. [Citation Graph (0, 0)][DBLP] CASES, 2007, pp:257-266 [Conf]
- Ravishankar Rao, Sarma B. K. Vrudhula
Energy optimal speed control of a producer--consumer device pair. [Citation Graph (0, 0)][DBLP] ACM Trans. Embedded Comput. Syst., 2007, v:6, n:4, pp:- [Journal]
Throughput optimal task allocation under thermal constraints for multi-core processors. [Citation Graph (, )][DBLP]
Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors. [Citation Graph (, )][DBLP]
Analytical results for design space exploration of multi-core processors employing thread migration. [Citation Graph (, )][DBLP]
Throughput of multi-core processors under thermal constraints. [Citation Graph (, )][DBLP]
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