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Yici Cai: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yici Cai, Zhu Pan, Sheldon X.-D. Tan, Xianlong Hong, Wenting Hou, Lifeng Wu
    Relaxed hierarchical power/ground grid analysis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1090-1093 [Conf]
  2. Haiyun Bao, Xianlong Hong, Yici Cai
    A New Global Routing Algorithm Independent Of Net Ordering. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:245-248 [Conf]
  3. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
    A buffer planning algorithm with congestion optimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:615-620 [Conf]
  4. Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan
    A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:505-510 [Conf]
  5. Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan
    VLSI on-chip power/ground network optimization considering decap leakage currents. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:735-738 [Conf]
  6. Wenting Hou, Hong Yu, Xianlong Hong, Yici Cai, Weimin Wu, Jun Gu, William H. Kao
    A new congestion-driven placement algorithm based on cell inflation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:605-608 [Conf]
  7. Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu
    Clock network minimization methodology based on incremental placement. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:99-102 [Conf]
  8. Gang Huang, Xianlong Hong, Changge Qiao, Yici Cai
    A Timing-Driven Block Placer Based on Sequence Pair Model. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:249-252 [Conf]
  9. Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong
    Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:582-587 [Conf]
  10. Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
    Register placement for low power clock network. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:588-593 [Conf]
  11. Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    VLSI floorplanning with boundary constraints based on corner block list. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:509-514 [Conf]
  12. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Buffer allocation algorithm with consideration of routing congestion. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:621-623 [Conf]
  13. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:387-392 [Conf]
  14. Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong
    Efficient early stage resonance estimation techniques for C4 package. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:826-831 [Conf]
  15. Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu
    An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:473-478 [Conf]
  16. Zhang Yan, Wang Baohua, Yici Cai, Xianlong Hong
    Area routing oriented hierarchical corner stitching with partial bin. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:105-110 [Conf]
  17. Hong Yu, Xianlong Hong, Yici Cai
    MMP: a novel placement algorithm for combined macro block and standard cell layout design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:271-276 [Conf]
  18. Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan
    Analysis of buffered hybrid structured clock networks. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:93-98 [Conf]
  19. Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong
    Partitioning-based approach to fast on-chip decap budgeting and minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:170-175 [Conf]
  20. Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
    Navigating registers in placement for clock network minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:176-181 [Conf]
  21. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Dynamic global buffer planning optimization based on detail block locating and congestion analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:806-811 [Conf]
  22. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:770-775 [Conf]
  23. Qinglang Luo, Xianlong Hong, Qiang Zhou, Yici Cai
    A new algorithm for layout of dark field alternating phase shifting masks. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:221-224 [Conf]
  24. Hailong Yao, Yici Cai, Xianlong Hong, Qiang Zhou
    Improved multilevel routing with redundant via placement for yield and reliability. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:143-146 [Conf]
  25. Xinjie Wei, Yici Cai, Xianlong Hong
    Physical aware clock skew rescheduling. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:473-476 [Conf]
  26. Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong Hong
    New timing and routability driven placement algorithms for FPGA synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:570-575 [Conf]
  27. Yanming Jia, Yici Cai, Xianlong Hong
    Dummy fill aware buffer insertion during routing. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:31-36 [Conf]
  28. Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu
    Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:8-12 [Conf]
  29. Xiaohai Wu, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai
    Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:153-157 [Conf]
  30. H. Yao, S. Sinha, C. Chiang, X. Hong, Y. Cai
    Efficient process-hotspot detection using range pattern matching. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:625-632 [Conf]
  31. Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan
    A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:344-349 [Conf]
  32. Yici Cai, Bin Liu, Xiong Yan, Qiang Zhou, Xianlong Hong
    A Hybrid Genetic Algorithm and Application to the Crosstalk Aware Track Assignment Problem. [Citation Graph (0, 0)][DBLP]
    ICNC (3), 2005, pp:181-184 [Conf]
  33. Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong
    Integrated routing resource assignment for RLC crosstalk minimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1871-1874 [Conf]
  34. Yici Cai, Yibo Wang, Xianlong Hong
    A global interconnect optimization algorithm under accurate delay model using solution space smoothing. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:93-96 [Conf]
  35. Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Evaluating a bounded slice-line grid assignment in O(nlogn) time. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:708-711 [Conf]
  36. Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani
    A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:6230-6233 [Conf]
  37. Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong
    Layer assignment algorithm for RLC crosstalk minimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:85-88 [Conf]
  38. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu
    Arbitrary convex and concave rectilinear block packing based on corner block list. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:493-496 [Conf]
  39. Yongqiang Lu, Xianlong Hong, Wenting Hou, Weimin Wu, Yici Cai
    Combining clustering and partitioning in quadratic placement. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:720-723 [Conf]
  40. Yang Wang, Yici Cai, Xianlong Hong, Qiang Zhou
    Algorithm for yield driven correction of layout. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:241-245 [Conf]
  41. Xinjie Wei, Yici Cai, Xianlong Hong
    Zero skew clock routing with tree topology construction using simulated annealing method. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:101-104 [Conf]
  42. Changqi Yang, Xianlong Hong, Hannah Honghua Yang, Qiang Zhou, Yici Cai, Yongqiang Lu
    Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:81-84 [Conf]
  43. Hailong Yao, Qiang Zhou, Xianlong Hong, Yici Cai
    Crosstalk driven routing resource assignment. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:89-92 [Conf]
  44. Yiqian Zhang, Xianlong Hong, Yici Cai
    An efficient algorithm for buffered routing tree construction under fixed buffer locations with accurate delay models. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:97-100 [Conf]
  45. Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong, Lei He, Jinjun Xiong
    Shielding area optimization under the solution of interconnect crosstalk. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:297-300 [Conf]
  46. Meng Zhao, Xinjie Wei, Yici Cai, Xianlong Hong
    Quick and effective buffered legitimate skew clock routing. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:337-340 [Conf]
  47. Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Jun Gu
    A novel and efficient timing-driven global router for standard cell layout design based on critical network concept. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:165-168 [Conf]
  48. Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
    An integrated floorplanning with an efficient buffer planning algorithm. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:136-142 [Conf]
  49. Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong
    High accurate pattern based precondition method for extremely large power/ground grid analysis. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:108-113 [Conf]
  50. Jeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
    Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:272-277 [Conf]
  51. Zhu Pan, Yici Cai, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong
    Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:63-68 [Conf]
  52. Zhenyu Qi, Hang Li, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong
    Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:542-547 [Conf]
  53. Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu
    Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:299-304 [Conf]
  54. Xinjie Wei, Yici Cai, Xianlong Hong
    Clock Skew Scheduling Under Process Variations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:237-242 [Conf]
  55. Yici Cai, Bin Liu, Jin Shi, Qiang Zhou, Xianlong Hong
    Power Delivery Aware Floorplanning for Voltage Island Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:350-355 [Conf]
  56. Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
    Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:383-388 [Conf]
  57. Hailong Yao, Yici Cai, Xianlong Hong
    CMP-aware Maze Routing Algorithm for Yield Enhancement. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:239-244 [Conf]
  58. Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan
    Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:433-441 [Conf]
  59. Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong
    A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:257-266 [Conf]
  60. Jin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan
    Efficient Simulation of Power/Ground Networks with Package and Vias. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:318-328 [Conf]
  61. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:387-392 [Conf]
  62. Yibo Wang, Yici Cai, Xianlong Hong
    A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:91-96 [Conf]
  63. Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu
    An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:473-478 [Conf]
  64. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Floorplanning with abutment constraints based on corner block list. [Citation Graph (0, 0)][DBLP]
    Integration, 2001, v:31, n:1, pp:65-77 [Journal]
  65. Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu
    An efficient hierarchical timing-driven Steiner tree algorithm for global routing. [Citation Graph (0, 0)][DBLP]
    Integration, 2003, v:35, n:2, pp:69-84 [Journal]
  66. Sheqin Dong, Shuo Zhou, Xianlong Hong, Chung-Kuan Cheng, Jun Gu, Yici Cai
    An Optimum Placement Search Algorithm Based on Extended Corner Block List. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2002, v:17, n:6, pp:699-707 [Journal]
  67. Yici Cai, Jin Shi, Zuying Luo, Xianlong Hong
    Modeling and Analysis of Mesh Tree Hybrid Power/Ground Networks with Multiple Voltage Supply in Time Domain. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:2, pp:224-230 [Journal]
  68. Yici Cai, Xin Zhao, Qiang Zhou, Xianlong Hong
    Shielding Area Optimization Under the Solution of Interconnect Crosstalk. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:6, pp:901-906 [Journal]
  69. Wenting Hou, Xianlong Hong, Weimin Wu, Yici Cai
    FaSa: A Fast and Stable Quadratic Placement Algorithm. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2003, v:18, n:3, pp:318-324 [Journal]
  70. Hailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong
    Crosstalk-Aware Routing Resource Assignment. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:2, pp:231-236 [Journal]
  71. Yici Cai, Bin Liu, Yan Xiong, Qiang Zhou, Xianlong Hong
    Priority-Based Routing Resource Assignment Considering Crosstalk. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2006, v:21, n:6, pp:913-921 [Journal]
  72. Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong
    Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2402-2412 [Journal]
  73. Xiaohai Wu, Xianlong Hong, Yici Cai, Zuying Luo, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai
    Area minimization of power distribution network using efficient nonlinear programming techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1086-1094 [Journal]
  74. Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu
    Stairway compaction using corner block list and its applications with rectilinear blocks. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:2, pp:199-211 [Journal]
  75. Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
    Statistical model order reduction for interconnect circuits considering spatial correlations. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1508-1513 [Conf]
  76. Yanfeng Wang, Qiang Zhou, Xianlong Hong, Yici Cai
    Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2040-2043 [Conf]
  77. Xinjie Wei, Yici Cai, Xianlong Hong
    Effective Acceleration of Iterative Slack Distribution Process. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1077-1080 [Conf]
  78. Yibo Wang, Yici Cai, Xianlong Hong
    Performance and power aware buffered tree construction. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  79. Weixiang Shen, Yici Cai, Jiang Hu, Xianlong Hong, Bing Lu
    High performance clock routing in X-architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  80. Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong
    A novel low-power physical design methodology for MTCMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  81. Lijuan Luo, Qiang Zhou, Yici Cai, Xianlong Hong, Yibo Wang
    A novel technique integrating buffer insertion into timing driven placement. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  82. Hailong Yao, Yici Cai, Xianlong Hong
    Congestion-driven W-shape multilevel full-chip routing framework. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  83. Yongqiang Lu, Xianlong Hong, Qiang Zhou, Yici Cai, Jun Gu
    An efficient quadratic placement based on search space traversing technology. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:3, pp:253-260 [Journal]
  84. Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
    Partitioning-based decoupling capacitor budgeting via sequence of linear programming. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:516-524 [Journal]
  85. Qiang Zhou, Yici Cai, Duo Li, Xianlong Hong
    A Yield-Driven Gridless Router. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2007, v:22, n:5, pp:653-660 [Journal]
  86. Xinjie Wei, Yici Cai, Meng Zhao, Xianlong Hong
    Legitimate Skew Clock Routing with Buffer Insertion. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:42, n:2, pp:107-116 [Journal]

  87. Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. [Citation Graph (, )][DBLP]


  88. Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos. [Citation Graph (, )][DBLP]


  89. Heuristic power/ground network and floorplan co-design method. [Citation Graph (, )][DBLP]


  90. Logic and Layout Aware Voltage Island Generation for Low Power Design. [Citation Graph (, )][DBLP]


  91. Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach. [Citation Graph (, )][DBLP]


  92. Vertical via design techniques for multi-layered P/G networks. [Citation Graph (, )][DBLP]


  93. Low power clock buffer planning methodology in F-D placement for large scale circuit design. [Citation Graph (, )][DBLP]


  94. GPU friendly fast Poisson solver for structured power grid network analysis. [Citation Graph (, )][DBLP]


  95. An efficient decoupling capacitance optimization using piecewise polynomial models. [Citation Graph (, )][DBLP]


  96. SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal. [Citation Graph (, )][DBLP]


  97. Fast congestion-aware timing-driven placement for island FPGA. [Citation Graph (, )][DBLP]


  98. MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. [Citation Graph (, )][DBLP]


  99. A novel performance driven power gating based on distributed sleep transistor network. [Citation Graph (, )][DBLP]


  100. Scaling power/ground solvers on multi-core with memory bandwidth awareness. [Citation Graph (, )][DBLP]


  101. Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks. [Citation Graph (, )][DBLP]


  102. Decoupling capacitance efficient placement for reducing transient power supply noise. [Citation Graph (, )][DBLP]


  103. Gate planning during placement for gated clock network. [Citation Graph (, )][DBLP]


  104. Leakage power optimization for clock network using dual-Vth technology. [Citation Graph (, )][DBLP]


  105. Analog circuit shielding routing algorithm based on net classification. [Citation Graph (, )][DBLP]


  106. Activity and register placement aware gated clock network design. [Citation Graph (, )][DBLP]


  107. DFM Based Detailed Routing Algorithm for ECP and CMP. [Citation Graph (, )][DBLP]


  108. Cell shifting aware of wirelength and overlap. [Citation Graph (, )][DBLP]


  109. Useful clock skew optimization under a multi-corner multi-mode design framework. [Citation Graph (, )][DBLP]


  110. A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation. [Citation Graph (, )][DBLP]


  111. Full-chip routing system for reducing Cu CMP & ECP variation. [Citation Graph (, )][DBLP]


  112. Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials. [Citation Graph (, )][DBLP]


  113. DFM-aware Routing for Yield Enhancement. [Citation Graph (, )][DBLP]


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