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## Search the dblp DataBase
Sheldon X.-D. Tan:
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## Publications of Author- Yici Cai, Zhu Pan, Sheldon X.-D. Tan, Xianlong Hong, Wenting Hou, Lifeng Wu
**Relaxed hierarchical power/ground grid analysis.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:1090-1093 [Conf] - Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan
**A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2004, pp:505-510 [Conf] - Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan
**VLSI on-chip power/ground network optimization considering decap leakage currents.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:735-738 [Conf] - Zhenyu Qi, Sheldon X.-D. Tan, Hao Yu, Lei He
**Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:224-229 [Conf] - Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong
**Efficient early stage resonance estimation techniques for C4 package.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2006, pp:826-831 [Conf] - Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan
**A wideband hierarchical circuit reduction for massively coupled interconnects.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:111-114 [Conf] - Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan
**Analysis of buffered hybrid structured clock networks.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:93-98 [Conf] - Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong
**Partitioning-based approach to fast on-chip decap budgeting and minimization.**[Citation Graph (0, 0)][DBLP] DAC, 2005, pp:170-175 [Conf] - Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
**Dynamic FPGA routing for just-in-time FPGA compilation.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:954-959 [Conf] - Sheldon X.-D. Tan, Weikun Guo, Zhenyu Qi
**Hierarchical approach to exact symbolic analysis of large analog circuits.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:860-863 [Conf] - Sheldon X.-D. Tan, C.-J. Richard Shi
**Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling.**[Citation Graph (0, 0)][DBLP] DAC, 2001, pp:550-554 [Conf] - Wei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon X.-D. Tan
**A systematic method for functional unit power estimation in microprocessors.**[Citation Graph (0, 0)][DBLP] DAC, 2006, pp:554-557 [Conf] - Sheldon X.-D. Tan, Zhenyu Qi, Hang Li
**Hierarchical Modeling and Simulation of Large Analog Circuits.**[Citation Graph (0, 0)][DBLP] DATE, 2004, pp:740-741 [Conf] - Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
**A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation.**[Citation Graph (0, 0)][DBLP] FCCM, 2005, pp:57-62 [Conf] - Pu Liu, Zhenyu Qi, Hang Li, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang
**Fast thermal simulation for architecture level dynamic thermal management.**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:639-644 [Conf] - Pu Liu, Sheldon X.-D. Tan, Hang Li, Zhenyu Qi, Jun Kong, Bruce McGaughy, Lei He
**An efficient method for terminal reduction of interconnect circuits considering delay variations.**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:821-826 [Conf] - Sheldon X.-D. Tan
**A General S-Domain Hierarchical Network Reduction Algorithm.**[Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:650-657 [Conf] - Hang Li, Pu Liu, Zhenyu Qi, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang
**Efficient Thermal Simulation for Run-Time Temperature Tracking and Management.**[Citation Graph (0, 0)][DBLP] ICCD, 2005, pp:130-136 [Conf] - Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan
**A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network.**[Citation Graph (0, 0)][DBLP] ICCD, 2004, pp:344-349 [Conf] - Weikun Guo, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong
**Partial random walk for large linear network analysis.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2004, pp:173-177 [Conf] - Junjie Yang, Sheldon X.-D. Tan
**Behavioural modelling of analog circuits by dynamic semi-symbolic analysis.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2004, pp:105-108 [Conf] - Junjie Yang, Sheldon X.-D. Tan
**An efficient algorithm for transient and distortion analysis of mildly nonlinear analog circuits.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2004, pp:129-132 [Conf] - Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan
**Efficient decoupling capacitor planning via convex programming methods.**[Citation Graph (0, 0)][DBLP] ISPD, 2006, pp:102-107 [Conf] - Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong
**High accurate pattern based precondition method for extremely large power/ground grid analysis.**[Citation Graph (0, 0)][DBLP] ISPD, 2006, pp:108-113 [Conf] - Jeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
**Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming.**[Citation Graph (0, 0)][DBLP] ISQED, 2006, pp:272-277 [Conf] - Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan
**SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching.**[Citation Graph (0, 0)][DBLP] ISQED, 2006, pp:638-643 [Conf] - Pu Liu, Zhenyu Qi, Sheldon X.-D. Tan
**Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits.**[Citation Graph (0, 0)][DBLP] ISQED, 2005, pp:603-608 [Conf] - Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng Wu
**Compact Reduced Order Modeling for Multiple-Port Interconnects.**[Citation Graph (0, 0)][DBLP] ISQED, 2006, pp:413-418 [Conf] - Zhu Pan, Yici Cai, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong
**Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling.**[Citation Graph (0, 0)][DBLP] ISQED, 2004, pp:63-68 [Conf] - Zhenyu Qi, Hang Li, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong
**Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery.**[Citation Graph (0, 0)][DBLP] ISQED, 2005, pp:542-547 [Conf] - Qi-De Qian, Sheldon X.-D. Tan
**Advanced Physical Models for Mask Data Verification and Impacts on Physical Layout Synthesis.**[Citation Graph (0, 0)][DBLP] ISQED, 2003, pp:125-130 [Conf] - Ning Mi, Boyuan Yan, Sheldon X.-D. Tan, Jeffrey Fan, Hao Yu
**General Block Structure-Preserving Reduced Order Modeling of Linear Dynamic Circuits.**[Citation Graph (0, 0)][DBLP] ISQED, 2007, pp:633-638 [Conf] - Boyuan Yan, Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy
**Passive Modeling of Interconnects by Waveform Shaping.**[Citation Graph (0, 0)][DBLP] ISQED, 2007, pp:356-361 [Conf] - Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan
**Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery.**[Citation Graph (0, 0)][DBLP] PATMOS, 2004, pp:433-441 [Conf] - Jin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan
**Efficient Simulation of Power/Ground Networks with Package and Vias.**[Citation Graph (0, 0)][DBLP] PATMOS, 2005, pp:318-328 [Conf] - Sheldon X.-D. Tan, C.-J. Richard Shi
**Balanced multi-level multi-way partitioning of analog integrated circuits for hierarchical symbolic analysis.**[Citation Graph (0, 0)][DBLP] Integration, 2003, v:34, n:1-2, pp:65-86 [Journal] - Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong
**Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2402-2412 [Journal] - Sheldon X.-D. Tan
**A general hierarchical circuit modeling and simulation algorithm.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:418-434 [Journal] - Zhenyu Qi, Hao Yu, Pu Liu, Sheldon X.-D. Tan, Lei He
**Wideband passive multiport model order reduction and realization of RLCM circuits.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1496-1509 [Journal] - C.-J. Richard Shi, Sheldon X.-D. Tan
**Canonical symbolic analysis of large analog circuits withdeterminant decision diagrams.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:1-18 [Journal] - C.-J. Richard Shi, Sheldon X.-D. Tan
**Compact representation and efficient generation of s-expandedsymbolic network functions for computer-aided analog circuit design.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:7, pp:813-827 [Journal] - Sheldon X.-D. Tan, Weikun Guo, Zhenyu Qi
**Hierarchical approach to exact symbolic analysis of large analog circuits.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1241-1250 [Journal] - Sheldon X.-D. Tan, C.-J. Richard Shi
**Hierarchical symbolic analysis of analog integrated circuits viadeterminant decision diagrams.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:4, pp:401-412 [Journal] - Sheldon X.-D. Tan, C.-J. Richard Shi
**Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:277-284 [Journal] - Sheldon X.-D. Tan, C.-J. Richard Shi
**Efficient approximation of symbolic expressions for analog behavioral modeling and analysis.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:907-918 [Journal] - Sheldon X.-D. Tan, C.-J. Richard Shi, Jyh-Chwen Lee
**Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:12, pp:1678-1684 [Journal] - Boyuan Yan, Sheldon X.-D. Tan, Pu Liu, Bruce McGaughy
**SBPOR: Second-Order Balanced Truncation for Passive Order Reduction of RLC Circuits.**[Citation Graph (0, 0)][DBLP] DAC, 2007, pp:158-161 [Conf] - Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
**Statistical model order reduction for interconnect circuits considering spatial correlations.**[Citation Graph (0, 0)][DBLP] DATE, 2007, pp:1508-1513 [Conf] - Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong
**Partitioning-based decoupling capacitor budgeting via sequence of linear programming.**[Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:4, pp:516-524 [Journal] - Wei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon X.-D. Tan
**Efficient power modeling and software thermal sensing for runtime temperature monitoring.**[Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal] - Bao Liu, Sheldon X.-D. Tan
**Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidefinite and Linear Programs.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1284-1287 [Journal] **Statistical modeling and analysis of chip-level leakage power by spectral stochastic method.**[Citation Graph (, )][DBLP]**Statistical analysis of on-chip power grid networks by variational extended truncated balanced realization method.**[Citation Graph (, )][DBLP]**Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos.**[Citation Graph (, )][DBLP]**Hierarchical Krylov subspace reduced order modeling of large RLC circuits.**[Citation Graph (, )][DBLP]**Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor Form.**[Citation Graph (, )][DBLP]**Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach.**[Citation Graph (, )][DBLP]**Architecture-level thermal behavioral characterization for multi-core microprocessors.**[Citation Graph (, )][DBLP]**Fast analysis of nontree-clock network considering environmental uncertainty by parameterized and incremental macromodeling.**[Citation Graph (, )][DBLP]**DeMOR: decentralized model order reduction of linear networks with massive ports.**[Citation Graph (, )][DBLP]**GPU friendly fast Poisson solver for structured power grid network analysis.**[Citation Graph (, )][DBLP]**A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation.**[Citation Graph (, )][DBLP]**A robust periodic arnoldi shooting algorithm for efficient analysis of large-scale RF/MM ICs.**[Citation Graph (, )][DBLP]**ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis.**[Citation Graph (, )][DBLP]**An efficient decoupling capacitance optimization using piecewise polynomial models.**[Citation Graph (, )][DBLP]**General behavioral thermal modeling and characterization for multi-core microprocessor design.**[Citation Graph (, )][DBLP]**Variational capacitance modeling using orthogonal polynomial method.**[Citation Graph (, )][DBLP]**FEKIS: a fast architecture-level thermal analyzer for online thermal regulation.**[Citation Graph (, )][DBLP]**A linear statistical analysis for full-chip leakage power with spatial correlation.**[Citation Graph (, )][DBLP]**Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks.**[Citation Graph (, )][DBLP]**Parameterized transient thermal behavioral modeling for chip multiprocessors.**[Citation Graph (, )][DBLP]**Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method.**[Citation Graph (, )][DBLP]**Decoupling capacitance efficient placement for reducing transient power supply noise.**[Citation Graph (, )][DBLP]**Improving the reliability of on-chip data caches under process variations.**[Citation Graph (, )][DBLP]**Statistical Analysis of Power Grid Networks Considering Lognormal Leakage Current Variations with Spatial Correlation.**[Citation Graph (, )][DBLP]**Voltage drop reduction for on-chip power delivery considering leakage current variations.**[Citation Graph (, )][DBLP]**Statistic Analysis of Power/Ground Networks Using Single-Node SOR Method.**[Citation Graph (, )][DBLP]**Statistical decoupling capacitance allocation by efficient numerical quadrature method.**[Citation Graph (, )][DBLP]
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