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Publications of Author

1. Yici Cai, Zhu Pan, Sheldon X.-D. Tan, Xianlong Hong, Wenting Hou, Lifeng Wu
   Relaxed hierarchical power/ground grid analysis. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:1090-1093 [Conf]
   
2. Yoshiyuki Kawakami, Jingkun Fang, Hirokazu Yonezawa, Nobufusa Iwanishi, Lifeng Wu, Alvin I-Hsien Chen, Norio Koike, Ping Chen, Chune-Sin Yeh, Zhihong Liu
   Gate-level aged timing simulation methodology for hot-carrier reliability assurance. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2000, pp:289-294 [Conf]
   
3. Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong
   Partitioning-based approach to fast on-chip decap budgeting and minimization. [Citation Graph (0, 0)][DBLP]
   DAC, 2005, pp:170-175 [Conf]
   
4. Lifeng Wu, Zhilian Yang, Zhiping Yu, Zhijian Li
   GOALSERVER: A Multiobjective Design Optimization Tool for IC Fabrication Process. [Citation Graph (0, 0)][DBLP]
   DAC, 1991, pp:585-590 [Conf]
   
5. Lifeng Wu
   NBTI/HCI Modeling and Full-Chip Analysis in Design Environment. [Citation Graph (0, 0)][DBLP]
   ISQED, 2003, pp:13-14 [Conf]
   
6. Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng Wu
   Compact Reduced Order Modeling for Multiple-Port Interconnects. [Citation Graph (0, 0)][DBLP]
   ISQED, 2006, pp:413-418 [Conf]
   
7. Zhenyu Qi, Hang Li, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong
   Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery. [Citation Graph (0, 0)][DBLP]
   ISQED, 2005, pp:542-547 [Conf]
   
8. Lifeng Wu, Jingkun Fang, Heting Yan, Ping Chen, Alvin I-Hsien Chen, Yoshifumi Okamoto, Chune-Sin Yeh, Zhihong Liu, Nobufusa Iwanishi, Norio Koike, Hirokazu Yonezawa, Yoshiyuki Kawakami
   GLACIER: A Hot Carrier Gate Level Circuit Characterization and Simulation System for VLSI Design. [Citation Graph (0, 0)][DBLP]
   ISQED, 2000, pp:73-80 [Conf]
   
9. Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong
   Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2402-2412 [Journal]
   
10. Lifeng Wu, Zhihong Liu
    Full-Chip Reliability Simulation for VDSM Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1273-1278 [Journal]
    
11. 
    Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method. [Citation Graph (, )][DBLP]
    
    
12. 
    Fitting Gompertz Curve Using Grey Method. [Citation Graph (, )][DBLP]