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Anirudh Devgan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kanak Agarwal, Dennis Sylvester, David Blaauw, Anirudh Devgan
    Achieving continuous VT performance in a dual VT process. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:393-398 [Conf]
  2. David Blaauw, Anirudh Devgan, Farid N. Najm
    Leakage power: trends, analysis and avoidance. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:- [Conf]
  3. Anirudh Devgan, Sandip Kundu
    Timing Analysis and Optimization: From Devices to Systems (Abstract of Embedded Tutorial). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:345- [Conf]
  4. Hao Ji, Anirudh Devgan, Wayne Wei-Ming Dai
    KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:379-384 [Conf]
  5. Anand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan
    Robust analytical gate delay modeling for low voltage circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:61-66 [Conf]
  6. Anand Ramalingam, Bin Zhang, Anirudh Devgan, David Z. Pan
    Sleep transistor sizing using timing criticality and temporal currents. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1094-1097 [Conf]
  7. Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan
    Delay and slew metrics using the lognormal distribution. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:382-385 [Conf]
  8. Charles J. Alpert, Anirudh Devgan
    Wire Segmenting for Improved Buffer Insertion. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:588-593 [Conf]
  9. Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
    Buffer Insertion for Noise and Delay Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:362-367 [Conf]
  10. Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
    Buffer Insertion with Accurate Gate and Interconnect Delay Computation. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:479-484 [Conf]
  11. Michael W. Beattie, Hui Zheng, Anirudh Devgan, Byron Krauter
    Spatially distributed 3D circuit models. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:153-158 [Conf]
  12. Murari Mani, Anirudh Devgan, Michael Orshansky
    An efficient algorithm for statistical minimization of total power under timing yield constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:309-314 [Conf]
  13. Tuyen V. Nguyen, Anirudh Devgan, Ognen J. Nastov
    Adjoint Transient Sensitivity Computation in Piecewise Linear Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:477-482 [Conf]
  14. Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester
    Parametric yield estimation considering leakage variability. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:442-447 [Conf]
  15. Florentin Dartu, Anirudh Devgan, Noel Menezes
    Variability modeling and variability-aware design in deep submicron integrated circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:1- [Conf]
  16. Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
    Is wire tapering worthwhile? [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:430-436 [Conf]
  17. Anirudh Devgan
    Efficient and accurate transient simulation in charge-voltage plane. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:110-114 [Conf]
  18. Anirudh Devgan
    Efficient coupled noise estimation for on-chip interconnects. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:147-151 [Conf]
  19. Anirudh Devgan, Hao Ji, Wayne Wei-Ming Dai
    How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:150-155 [Conf]
  20. Anirudh Devgan, Chandramouli V. Kashyap
    Block-based Static Timing Analysis with Uncertainty. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:607-614 [Conf]
  21. Anirudh Devgan, Peter R. O'Brien
    Realizable reduction for RC interconnect circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:204-207 [Conf]
  22. Anirudh Devgan, Ronald A. Rohrer
    Event driven adaptively controlled explicit simulation of integrated circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:136-140 [Conf]
  23. Anirudh Devgan, Leon Stok, Sandip Kundu
    Timing analysis and optimization: from devices to systems (tutorial). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:- [Conf]
  24. Chandramouli V. Kashyap, Charles J. Alpert, Anirudh Devgan
    An "Effective" Capacitance Based Delay Metric for RC Interconnect. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:229-234 [Conf]
  25. Jiayong Le, Lawrence T. Pileggi, Anirudh Devgan
    Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:491-496 [Conf]
  26. Tuyen V. Nguyen, Anirudh Devgan
    State transformation in event driven explicit simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:289-294 [Conf]
  27. Tuyen V. Nguyen, Anirudh Devgan, Ali Sadigh
    Simulation of coupling capacitances using matrix partitioning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:12-18 [Conf]
  28. Anirudh Devgan
    Accurate device modeling techniques for efficient timing simulation of integrated circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:138-143 [Conf]
  29. Anirudh Devgan, Ronald A. Rohrer
    ACES: A Transient Simulation Strategy for Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:357-360 [Conf]
  30. Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns
    Leakage and leakage sensitivity computation for combinational circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:96-99 [Conf]
  31. Maha Nizam, Farid N. Najm, Anirudh Devgan
    Power grid voltage integrity verification. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:239-244 [Conf]
  32. Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown
    Efficient techniques for gate leakage estimation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:100-103 [Conf]
  33. Haihua Su, Frank Liu, Anirudh Devgan, Emrah Acar, Sani R. Nassif
    Full chip leakage estimation considering power supply and temperature variations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:78-83 [Conf]
  34. Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap
    A two moment RC delay metric for performance optimization. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:69-74 [Conf]
  35. Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
    Closed form expressions for extending step delay and slew metrics to ramp inputs. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:24-31 [Conf]
  36. Anirudh Devgan, Luca Daniel, Byron Krauter, Lei He
    Modeling and Design of Chip-Package Interface. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:6- [Conf]
  37. Anirudh Devgan, Ruchir Puri, Sachin Sapatnaker, Tanay Karnik, Rajiv V. Joshi
    Design of sub-90nm Circuits and Design Methodologies. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:3-4 [Conf]
  38. Rahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown
    Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:284-290 [Conf]
  39. Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
    PERI: a technique for extending delay and slew metrics to ramp inputs. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:57-62 [Conf]
  40. Anirudh Devgan, Sani R. Nassif
    Power Variability and Its Impact on Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:679-682 [Conf]
  41. Anirudh Devgan, Ronald A. Rohrer
    Efficient simulation of interconnect and mixed analog-digital circuits in ACES. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:229-233 [Conf]
  42. Rajeev R. Rao, David Blaauw, Dennis Sylvester, Anirudh Devgan
    Modeling and Analysis of Parametric Yield under Power and Performance Constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:376-385 [Journal]
  43. Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan
    Closed-form delay and slew metrics made easy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1661-1669 [Journal]
  44. Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay
    Interconnect synthesis without wire tapering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:90-104 [Journal]
  45. Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay
    Correction to "interconnect synthesis without wire tapering". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:497-497 [Journal]
  46. Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap
    RC delay metrics for performance optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:571-582 [Journal]
  47. Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
    Buffer insertion for noise and delay optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1633-1645 [Journal]
  48. Anirudh Devgan
    Transient simulation of integrated circuits in the charge-voltage plane. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:11, pp:1379-1390 [Journal]
  49. Anirudh Devgan, Ronald A. Rohrer
    Adaptively controlled explicit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:746-762 [Journal]
  50. Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
    Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:509-516 [Journal]
  51. Tuyen V. Nguyen, Anirudh Devgan, Ognen J. Nastov, David W. Winston
    Transient sensitivity computation in controlled explicit piecewiselinear simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:98-110 [Journal]
  52. Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester
    Analytical yield prediction considering leakage/performance correlation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1685-1695 [Journal]
  53. Emrah Acar, Anirudh Devgan, Sani R. Nassif
    Leakage and Leakage Sensitivity Computation for Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:2, pp:172-181 [Journal]
  54. Anand Ramalingam, Anirudh Devgan, David Z. Pan
    Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:28-35 [Journal]

  55. Reinventing EDA with manycore processors. [Citation Graph (, )][DBLP]


  56. Accelerated design of analog, mixed-signal circuits in Titan. [Citation Graph (, )][DBLP]


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