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## Search the dblp DataBase
Janet Meiling Wang:
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## Publications of Author- Vineet Agarwal, Navneeth Kankani, Ravishankar Rao, Sarvesh Bhardwaj, Janet Wang
**An efficient combinationality check technique for the synthesis of cyclic combinational circuits.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:212-215 [Conf] - Vineet Agarwal, Janet Meiling Wang
**Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA).**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2006, pp:718-723 [Conf] - Navneeth Kankani, Vineet Agarwal, Janet Meiling Wang
**A probabilistic analysis of pipelined global interconnect under process variations.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2006, pp:724-729 [Conf] - Janet Meiling Wang, Omar Hafiz, Pinhong Chen
**A non-iterative model for switching window computation with crosstalk noise.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2004, pp:846-851 [Conf] - Janet Meiling Wang, Prashant Saxena, Omar Hafiz, Xing Wang
**Realizable parasitic reduction for distributed interconnects using matrix pencil technique.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2004, pp:780-785 [Conf] - Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wang
**A methodology to improve timing yield in the presence of process variations.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:448-453 [Conf] - Janet Meiling Wang, Omar Hafiz, Jun Li
**A linear fractional transform (LFT) based model for interconnect parametric uncertainty.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:375-380 [Conf] - Janet Meiling Wang, Tuyen V. Nguyen
**Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources.**[Citation Graph (0, 0)][DBLP] DAC, 2000, pp:247-252 [Conf] - Qingjian Yu, Janet Meiling Wang, Ernest S. Kuh
**Passive model order reduction algorithm based on Chebyshev expansion of impulse response of interconnect networks.**[Citation Graph (0, 0)][DBLP] DAC, 2000, pp:520-525 [Conf] - Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Meiling Wang
**Stochastic Power Grid Analysis Considering Process Variations.**[Citation Graph (0, 0)][DBLP] DATE, 2005, pp:964-969 [Conf] - Y. Satish Kumar, Jun Li, Claudio Talarico, Janet Meiling Wang
**A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching.**[Citation Graph (0, 0)][DBLP] DATE, 2005, pp:770-775 [Conf] - Bharat B. Sukhwani, Uday Padmanabhan, Janet Meiling Wang
**Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design.**[Citation Graph (0, 0)][DBLP] DATE, 2005, pp:758-763 [Conf] - Janet Meiling Wang, Qingjian Yu, Ernest S. Kuh
**Coupled Noise Estimation for Distributed RC Interconnect Model.**[Citation Graph (0, 0)][DBLP] DATE, 1999, pp:664-668 [Conf] - Rong Jiang, Wenyin Fu, Janet Meiling Wang, Vince Lin, Charlie Chung-Ping Chen
**Efficient statistical capacitance variability modeling with orthogonal principle factor analysis.**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:683-690 [Conf] - Jun-Fa Mao, Janet Meiling Wang, Ernest S. Kuh
**Simulation and sensitivity analysis of transmission line circuits by the characteristics method.**[Citation Graph (0, 0)][DBLP] ICCAD, 1996, pp:556-562 [Conf] - Janet Meiling Wang, Praveen Ghanta, Sarma B. K. Vrudhula
**Stochastic analysis of interconnect performance in the presence of process variations.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:880-886 [Conf] - Janet Meiling Wang, Ernest S. Kuh, Qingjian Yu
**The Chebyshev expansion based passive model for distributed interconnect networks.**[Citation Graph (0, 0)][DBLP] ICCAD, 1999, pp:370-375 [Conf] - Janet Meiling Wang, Bharat Srinivas, Dongsheng Ma, Charlie Chung-Ping Chen, Jun Li
**System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS).**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:728-735 [Conf] - Qingjian Yu, Janet Meiling Wang, Ernest S. Kuh
**Multipoint moment matching model for multiport distributed interconnect networks.**[Citation Graph (0, 0)][DBLP] ICCAD, 1998, pp:85-91 [Conf] - Kishore Kumar Muchherla, Pinhong Chen, Janet Meiling Wang
**A non-iterative equivalent waveform model for timing analysis in presence of crosstalk.**[Citation Graph (0, 0)][DBLP] ISCAS (3), 2005, pp:2465-2468 [Conf] - Bharat B. Sukhwani, Janet Meiling Wang
**A stepwise constant conductance approach for simulating resonant tunneling diodes.**[Citation Graph (0, 0)][DBLP] ISCAS (3), 2005, pp:2518-2521 [Conf] - Lakshmi Kalpana Vakati, Janet Meiling Wang
**A new multi-ramp driver model with RLC interconnect load.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2004, pp:269-272 [Conf] - Janet Meiling Wang, Omar Hafiz
**Matrix pencil based realizable reduction for distributed interconnects.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2004, pp:177-180 [Conf] - Satish K. Yanamanamanda, Jun Li, Janet Meiling Wang
**Uncertainty modeling of gate delay considering multiple input switching.**[Citation Graph (0, 0)][DBLP] ISCAS (3), 2005, pp:2457-2460 [Conf] - Omar Hafiz, Pinhong Chen, Janet Wang
**A new non-iterative model for switching window computation with crosstalk noise.**[Citation Graph (0, 0)][DBLP] ISCAS (2), 2004, pp:497-500 [Conf] - Dongsheng Ma, Janet Meiling Wang, Mohankumar N. Somasundaram, Zongqi Hu
**Design and optimization on dynamic power system for self-powered integrated wireless sensing nodes.**[Citation Graph (0, 0)][DBLP] ISLPED, 2005, pp:303-306 [Conf] - Dongsheng Ma, Janet Meiling Wang, Pablo Vazquas
**Adaptive on-chip power supply with robust one-cycle control technique.**[Citation Graph (0, 0)][DBLP] ISLPED, 2006, pp:394-399 [Conf] - Uday Padmanabhan, Janet Meiling Wang, Jiang Hu
**Statistical clock tree routing for robustness to process variations.**[Citation Graph (0, 0)][DBLP] ISPD, 2006, pp:149-156 [Conf] - Lakshmi Kalpana Vakati, Janet Meiling Wang
**A new multi-ramp driver model with RLC interconnect load.**[Citation Graph (0, 0)][DBLP] ISPD, 2004, pp:170-175 [Conf] - Janet Meiling Wang, Omar Hafiz
**Predicting Interconnect Uncertainty with a New Robust Model Order Reduction Method.**[Citation Graph (0, 0)][DBLP] ISQED, 2004, pp:363-368 [Conf] - Janet Meiling Wang, Kishore Kumar Muchherla, Jai Ganesh Kumar
**A Clustering Based Area I/O Planning for Flip-Chip Technology.**[Citation Graph (0, 0)][DBLP] ISQED, 2004, pp:196-201 [Conf] - Janet Meiling Wang, Pinhong Chen, Omar Hafiz
**A New Continuous Switching Window Computation with Crosstalk Noise.**[Citation Graph (0, 0)][DBLP] SBCCI, 2003, pp:261-266 [Conf] - Janet Meiling Wang, Pinhong Chen, Omar Hafiz
**Switching Windows Computation in Presence of Crosstalk Noise.**[Citation Graph (0, 0)][DBLP] VLSI, 2003, pp:114-118 [Conf] - Yu-Min Lee, Yahong Cao, Tsung-Hao Chen, Janet Meiling Wang, Charlie Chung-Ping Chen
**HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:797-806 [Journal] - Sarma B. K. Vrudhula, Janet Meiling Wang, Praveen Ghanta
**Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2001-2011 [Journal] - Janet Meiling Wang, Jun Li, Satish K. Yanamanamanda, Lakshmi Kalpana Vakati, Kishore Kumar Muchherla
**Modeling the Driver Load in the Presence of Process Variations.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2264-2275 [Journal] - Alexander V. Mitev, Michael Marefat, Dongsheng Ma, Janet Meiling Wang
**Principle hessian direction based parameter reduction for interconnect networks with process variation.**[Citation Graph (0, 0)][DBLP] SLIP, 2007, pp:41-46 [Conf] - Bharat Sukhwani, Uday Padmanabhan, Janet Meiling Wang
**Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design**[Citation Graph (0, 0)][DBLP] CoRR, 2007, v:0, n:, pp:- [Journal] - Y. Satish Kumar, Jun Li, Claudio Talarico, Janet Wang
**A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching**[Citation Graph (0, 0)][DBLP] CoRR, 2007, v:0, n:, pp:- [Journal] - Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Wang
**Stochastic Power Grid Analysis Considering Process Variations**[Citation Graph (0, 0)][DBLP] CoRR, 2007, v:0, n:, pp:- [Journal] **Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures.**[Citation Graph (, )][DBLP]**Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method.**[Citation Graph (, )][DBLP]**Delay Uncertainty Reduction by Interconnect and Gate Splitting.**[Citation Graph (, )][DBLP]**Handling partial correlations in yield prediction.**[Citation Graph (, )][DBLP]**Chebyshev Affine Arithmetic based parametric yield prediction under limited descriptions of uncertainty.**[Citation Graph (, )][DBLP]**Principle Hessian direction based parameter reduction with process variation.**[Citation Graph (, )][DBLP]**A robust finite-point based gate model considering process variations.**[Citation Graph (, )][DBLP]**Robust interconnect communication capacity algorithm by geometric programming.**[Citation Graph (, )][DBLP]**Finite-Point Gate Model for Fast Timing and Power Analysis.**[Citation Graph (, )][DBLP]**Robust gate sizing by Uncertainty Second Order Cone.**[Citation Graph (, )][DBLP]**NBTI aware workload balancing in multi-core systems.**[Citation Graph (, )][DBLP]**Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs).**[Citation Graph (, )][DBLP]
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