The SCEAS System
Navigation Menu

Search the dblp DataBase


Leon Stok: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Raul Camposano, Olivier Coudert, Patrick Groeneveld, Leon Stok, Ralph H. J. M. Otten
    Timing closure: the solution and its problems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:359-364 [Conf]
  2. Ruchir Puri, Leon Stok, Subhrajit Bhattacharya
    Keeping hot chips cool. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:285-288 [Conf]
  3. Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni
    Pushing ASIC performance in a power envelope. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:788-793 [Conf]
  4. Wilm E. Donath, Prabhakar Kudva, Leon Stok, Paul Villarrubia, Lakshmi N. Reddy, Andrew Sullivan, Kanad Chakraborty
    Transformational Placement and Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:194-201 [Conf]
  5. Thomas Kutzschebauch, Leon Stok
    Layout Driven Decomposition with Congestion Consideration. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:672-676 [Conf]
  6. Leon Stok, Andrew J. Sullivan, Mahesh A. Iyer
    Wavefront Technology Mapping. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:531-0 [Conf]
  7. H. M. A. M. Arts, Jos T. J. van Eijndhoven, Leon Stok
    Flexible Block-Multiplier Generation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:106-109 [Conf]
  8. Frederik Beeftink, Prabhakar Kudva, David S. Kung, Leon Stok
    Gate-size selection for standard cell libraries. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:545-550 [Conf]
  9. Reinaldo A. Bergamaschi, Daniel Brand, Leon Stok, Michel R. C. M. Berkelaar, S. Prakash
    Efficient use of large don't cares in high-level and logic synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:272-278 [Conf]
  10. Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok
    Be careful with don't cares. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:83-86 [Conf]
  11. Anirudh Devgan, Leon Stok, Sandip Kundu
    Timing analysis and optimization: from devices to systems (tutorial). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:- [Conf]
  12. Thomas Kutzschebauch, Leon Stok
    Regularity Driven Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:439-446 [Conf]
  13. Thomas Kutzschebauch, Leon Stok
    Congestion Aware Layout Driven Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:216-223 [Conf]
  14. Leon Stok
    False loops through resource sharing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:345-348 [Conf]
  15. Ruchir Puri, David S. Kung, Leon Stok
    Minimizing power with flexible voltage islands. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:21-24 [Conf]
  16. Leon Stok, John Cohn
    There is life left in ASICs. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:48-50 [Conf]
  17. Frederik Beeftink, Prabhakar Kudva, David S. Kung, Ruchir Puri, Leon Stok
    Combinatorial cell design for CMOS libraries. [Citation Graph (0, 0)][DBLP]
    Integration, 2000, v:29, n:1, pp:67-93 [Journal]
  18. Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok
    Don't cares in synthesis: theoretical pitfalls and practical solutions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:4, pp:285-304 [Journal]
  19. Guy Even, Ilan Y. Spillinger, Leon Stok
    Retiming revisited and reversed. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:3, pp:348-357 [Journal]
  20. Soha Hassoun, Steven M. Nowick, Leon Stok
    Guest Editorial. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:662-664 [Journal]

  21. From restrictive to prescriptive design. [Citation Graph (, )][DBLP]

  22. EDA challenges and options: investing for the future. [Citation Graph (, )][DBLP]

  23. DAC Highlights. [Citation Graph (, )][DBLP]

  24. Variability and New Design Paradigms. [Citation Graph (, )][DBLP]

Search in 0.004secs, Finished in 0.005secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002