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Ralph H. J. M. Otten: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Raul Camposano, Olivier Coudert, Patrick Groeneveld, Leon Stok, Ralph H. J. M. Otten
    Timing closure: the solution and its problems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:359-364 [Conf]
  2. Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah
    Statistical timing for parametric yield prediction of digital integrated circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:932-937 [Conf]
  3. Dirk-Jan Jongeneel, Yosinori Watanabe, Robert K. Brayton, Ralph H. J. M. Otten
    Area and search space control for technology mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:86-91 [Conf]
  4. Ireneusz Karkowski, Ralph H. J. M. Otten
    Retiming Synchronous Circuitry with Imprecise Delays. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:322-326 [Conf]
  5. Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton, Ralph H. J. M. Otten, Alberto L. Sangiovanni-Vincentelli
    A Novel VLSI Layout Fabric for Deep Sub-Micron Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:491-496 [Conf]
  6. Ralph H. J. M. Otten, Robert K. Brayton
    Planning for Performance. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:122-127 [Conf]
  7. Bogdan G. Arsintescu, Ralph H. J. M. Otten
    Constraints Space Management for the Layout of Analog IC's. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:971-972 [Conf]
  8. Giuseppe S. Garcea, N. P. van der Meijs, Kees-Jan van der Kolk, Ralph H. J. M. Otten
    Statistically Aware Buffer Planning. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1402-1403 [Conf]
  9. Ralph H. J. M. Otten, Raul Camposano, Patrick Groeneveld
    Design Automation for Deepsubmicron: Present and Future. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:650-659 [Conf]
  10. Jurjen Westra, Dirk-Jan Jongeneel, Ralph H. J. M. Otten, Chandu Visweswariah
    Time Budgeting in a Wireplanning Context. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10436-10441 [Conf]
  11. Giuseppe S. Garcea, N. P. van der Meijs, Ralph H. J. M. Otten
    Simultaneous Analytic Area and Power Optimization for Repeater Insertion. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:568-573 [Conf]
  12. Ralph H. J. M. Otten, Lukas P. P. P. van Ginneken, Narendra V. Shenoy
    Embedded tutorial: Speed - new paradigms in design for performance. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:700- [Conf]
  13. Ralph H. J. M. Otten, Paul Stravers
    Challenges in Physical Chip Design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:84-91 [Conf]
  14. Serban Bruma, Ralph H. J. M. Otten
    Novel Simulation of Deep-Submicron MOSFET Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:62-67 [Conf]
  15. Ralph H. J. M. Otten
    What is a floorplan?. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:201-206 [Conf]
  16. Ralph H. J. M. Otten
    Global wires: harmful?. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:104-109 [Conf]
  17. Ralph H. J. M. Otten, Giuseppe S. Garcea
    Are wires plannable? [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:59-66 [Conf]
  18. Dirk-Jan Jongeneel, Ralph H. J. M. Otten
    Technology mapping for area and speed. [Citation Graph (0, 0)][DBLP]
    Integration, 2000, v:29, n:1, pp:45-66 [Journal]
  19. Ralph H. J. M. Otten
    Shifts in INTEGRATION: 20 years of VLSI design. [Citation Graph (0, 0)][DBLP]
    Integration, 2002, v:32, n:1-2, pp:1-4 [Journal]
  20. Ralph H. J. M. Otten, Robert K. Brayton
    Performance planning. [Citation Graph (0, 0)][DBLP]
    Integration, 2000, v:29, n:1, pp:1-24 [Journal]
  21. Hong Cai, Ralph H. J. M. Otten
    Conflict-free channel definition in building-block layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:9, pp:981-988 [Journal]
  22. Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah
    Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2376-2392 [Journal]

  23. Optimal slicing of plane point placements. [Citation Graph (, )][DBLP]


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