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Title:
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Michael L. Bushnell: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Vishwani D. Agrawal, Michael L. Bushnell
    T5: Electronic Testing for SOC Designers. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:20- [Conf]
  2. Vishwani D. Agrawal, Michael L. Bushnell, Qing Lin
    Redundancy Identification Using Transitive Closure. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:4-9 [Conf]
  3. Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell
    False-Path Removal Using Delay Fault Simulation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:82-87 [Conf]
  4. Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell
    Functional test generation for path delay faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:339-345 [Conf]
  5. Daniel R. Brasen, Michael L. Bushnell
    MHERTZ: A New Optimization Algorithm for Floorplanning and Global Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:107-110 [Conf]
  6. Michael L. Bushnell, Stephen W. Director
    VLSI CAD tool integration using the Ulysses environment. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:55-61 [Conf]
  7. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
    Delay Fault Models and Test Generation for Random Logic Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:165-172 [Conf]
  8. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
    Design for Testability for Path Delay faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:453-457 [Conf]
  9. Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell
    Automatic Test Generation Using Quadratic 0-1 Programming. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:654-659 [Conf]
  10. Xinghao Chen, Michael L. Bushnell
    A Module Area Estimator for VLSI Layout. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:54-59 [Conf]
  11. John Giraldi, Michael L. Bushnell
    EST: The New Frontier in Automatic Test-Pattern Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:667-672 [Conf]
  12. Keerthi Heragu, Michael L. Bushnell, Vishwani D. Agrawal
    An Efficient Path Delay Fault Coverage Estimator. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:516-521 [Conf]
  13. Vivek Gaur, Vishwani D. Agrawal, Michael L. Bushnell
    A New Transitive Closure Algorithm with Application to Redundancy Identification. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:496-500 [Conf]
  14. Sandip Parikh, David Sarnoff, Michael L. Bushnell, James Sienicki, Ramakrishnan Ganesh
    Distributed Computing, Automatic Design, and Error Recovery in the ULYSSES II Framework. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:610-617 [Conf]
  15. Xinghao Chen, Michael L. Bushnell
    Dynamic State and Objective Learning for Sequential Circuit Automatic Test Generation Using Decomposition Equivalence. [Citation Graph (0, 0)][DBLP]
    FTCS, 1994, pp:446-455 [Conf]
  16. Baozhen Yu, Michael L. Bushnell
    A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:214-219 [Conf]
  17. Michael L. Bushnell
    Increasing Test Coverage in a VLSI Design Course. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1133- [Conf]
  18. Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
    Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:139-148 [Conf]
  19. Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
    An Exact Non-Enumerative Fault Simulator for Path-Delay Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:276-285 [Conf]
  20. John Giraldi, Michael L. Bushnell
    Search State Equivalence for Redundancy Identification and Test Generation. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:184-193 [Conf]
  21. Omar I. Khan, Michael L. Bushnell
    Spectral Analysis for Statistical Response Compaction During Built-In Self-Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:67-76 [Conf]
  22. Carlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu
    A non-enumerative path delay fault simulator for sequential circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:934-943 [Conf]
  23. Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal
    Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:375-383 [Conf]
  24. Junwu Zhang, Michael L. Bushnell, Vishwani D. Agrawal
    On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:617-626 [Conf]
  25. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
    Design of Variable Input Delay Gates for Low Dynamic Power Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:436-445 [Conf]
  26. Vishwani D. Agrawal, Michael L. Bushnell
    Electronic Testing for SOC Designers (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:20- [Conf]
  27. Vishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss
    Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:434-439 [Conf]
  28. Shweta Chary, Michael L. Bushnell
    Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:413-418 [Conf]
  29. Shweta Chary, Michael L. Bushnell
    Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:818-823 [Conf]
  30. Xinghao Chen, Michael L. Bushnell
    Generation of search state equivalence for automatic test pattern generation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:99-103 [Conf]
  31. Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell
    Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:723-729 [Conf]
  32. Suresh Kumar Devanathan, Michael L. Bushnell
    Sequential Spectral ATPG Using the Wavelet Transform and Compaction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:407-412 [Conf]
  33. Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
    Parallel concurrent path-delay fault simulation using single-input change patterns. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:426-431 [Conf]
  34. Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell
    Statistical methods for delay fault coverage analysis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:166-170 [Conf]
  35. Omar I. Khan, Michael L. Bushnell
    Aliasing Analysis of Spectral Statistical Response Compaction Techniques. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:801-806 [Conf]
  36. Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal
    Path Delay Testing: Variable-Clock Versus Rated-Clock. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:470-475 [Conf]
  37. Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell
    A Complete Characterization of Path Delay Faults through Stuck-at Faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:492-497 [Conf]
  38. Vishal J. Mehta, Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell
    A Fault-Independent Transitive Closure Algorithm for Redundancy Identification. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:149-154 [Conf]
  39. Sanjay Mohan, Michael L. Bushnell
    A Code Transition Delay Model for ADC Test. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:274-282 [Conf]
  40. Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas
    Statistical path delay fault coverage estimation for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:290-295 [Conf]
  41. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
    Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:527-532 [Conf]
  42. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
    A Tuturial on the Emerging Nanotechnology Devices. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:343-360 [Conf]
  43. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
    CMOS Circuit Design for Minimum Dynamic Power and Highest Speed. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:1035-1040 [Conf]
  44. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
    Variable Input Delay CMOS Logic for Low Power Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:598-605 [Conf]
  45. Rajesh Ramadoss, Michael L. Bushnell
    Test generation for mixed-signal devices using signal flow graphs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:242-248 [Conf]
  46. Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal
    New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:353-360 [Conf]
  47. Imtiaz P. Shaik, Michael L. Bushnell
    A graph approach to DFT hardware placement for robust delay fault BIST. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:177-182 [Conf]
  48. James Sienicki, Michael L. Bushnell, Sandip Parikh
    Graphical Methodology Language for CAD Frameworks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:401-406 [Conf]
  49. James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal
    An asynchronous algorithm for sequential circuit test generation on a network of workstations. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:36-41 [Conf]
  50. Mandyam-Komar Srinivas, Michael L. Bushnell, Vishwani D. Agrawal
    Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:88-94 [Conf]
  51. Hari Vijay Venkatanarayanan, Michael L. Bushnell
    An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:161-168 [Conf]
  52. Rohit Pandey, Michael L. Bushnell
    Architecture for Variable-Length Combined FFT, DCT, and MWT Transform Hardware for a Multi-ModeWireless System. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:121-126 [Conf]
  53. Rajamani Sethuram, Omar I. Khan, Hari Vijay Venkatanarayanan, Michael L. Bushnell
    A Neural Net Branch Predictor to Reduce Power. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:679-684 [Conf]
  54. Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell
    Zero Cost Test Point Insertion Technique for Structured ASICs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:357-363 [Conf]
  55. Daniel Mazor, Michael L. Bushnell, David J. Mulligan, Richard J. Blaikie
    Fault Models and Device Yield of a Large Population of Room Temperature Operation Single-Electron Transistors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:657-664 [Conf]
  56. Jeffrey Ayres, Michael L. Bushnell
    Analog Circuit Testing Using Auto Regressive Moving Average Models. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:775-780 [Conf]
  57. Suresh Kumar Devanathan, Michael L. Bushnell
    Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:485-491 [Conf]
  58. Madhu K. Iyer, Michael L. Bushnell
    Effect of Noise on Analog Circuit Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:138-144 [Conf]
  59. Subhashis Majumder, Vishwani D. Agrawal, Michael L. Bushnell
    On Delay-Untestable Paths and Stuck-Fault Redundancy. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:194-199 [Conf]
  60. Ganapathy Parthasarathy, Michael L. Bushnell
    Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:210-217 [Conf]
  61. Imtiaz P. Shaik, Michael L. Bushnell
    Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming . [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:393-399 [Conf]
  62. Michael L. Bushnell, Stephen W. Director
    ULYSSES - a knowledge-based VLSI design environment. [Citation Graph (0, 0)][DBLP]
    AI in Engineering, 1987, v:2, n:1, pp:33-41 [Journal]
  63. Michael L. Bushnell, Pierre Haren
    Guest editorial. [Citation Graph (0, 0)][DBLP]
    AI in Engineering, 1986, v:1, n:2, pp:67-69 [Journal]
  64. Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell, Thomas K. Truong
    Neural Net and Boolean Satisfiability Models of Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1990, v:7, n:5, pp:54-57 [Journal]
  65. Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell
    A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2004, v:19, n:6, pp:955-964 [Journal]
  66. Michael L. Bushnell, Stephen W. Director
    Automated design tool execution in the Ulysses design environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:3, pp:279-287 [Journal]
  67. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
    On variable clock methods for path delay testing of sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1237-1249 [Journal]
  68. Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal
    Toward massively parallel automatic test generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:9, pp:981-994 [Journal]
  69. Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
    The path-status graph with application to delay fault simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:4, pp:324-332 [Journal]
  70. Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
    A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:873-876 [Journal]
  71. Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell
    Fault coverage estimation by test vector sampling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:590-596 [Journal]
  72. Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell, Janak H. Patel
    Improving a nonenumerative method to estimate path delay fault coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:759-762 [Journal]
  73. Baozhen Yu, Michael L. Bushnell
    Power Grid Analysis of Dynamic Power Cutoff Technology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1393-1396 [Conf]
  74. Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal
    Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1245-1255 [Journal]
  75. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
    Improving path delay testability of sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:736-741 [Journal]
  76. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
    Path delay fault simulation of sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:223-228 [Journal]
  77. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
    Transistor Sizing of Logic Gates to Maximize Input Delay Variability. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:1, pp:121-128 [Journal]

  78. An adaptive distributed algorithm for sequential circuit test generation. [Citation Graph (, )][DBLP]


  79. A Jitter Reduction Circuit Using Autocorrelation for Phase-Locked Loops and Serializer-Deserializer (SERDES) Circuits. [Citation Graph (, )][DBLP]


  80. Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults. [Citation Graph (, )][DBLP]


  81. A solvable class of quadratic 0-1 programming. [Citation Graph (, )][DBLP]


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