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Author:
Jiang Hu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ke Cao, Puneet Dhawan, Jiang Hu
    Library cell layout with Alt-PSM compliance and composability. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:216-219 [Conf]
  2. Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu
    Clock network minimization methodology based on incremental placement. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:99-102 [Conf]
  3. Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
    Making fast buffer insertion even faster via approximation techniques. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:13-18 [Conf]
  4. Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
    Register placement for low power clock network. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:588-593 [Conf]
  5. Cliff C. N. Sze, Jiang Hu, Charles J. Alpert
    A place and route aware buffered Steiner tree construction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:355-360 [Conf]
  6. Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu
    Skew scheduling and clock routing for improved tolerance to process variations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:594-599 [Conf]
  7. Di Wu, Jiang Hu, Rabi N. Mahapatra, Min Zhao
    Layer assignment for crosstalk risk minimization. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:159-162 [Conf]
  8. Di Wu, Jiang Hu, Min Zhao, Rabi N. Mahapatra
    Timing driven track routing considering coupling capacitance. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1156-1159 [Conf]
  9. Mike Brzozowski, Kendra Carattini, Scott R. Klemmer, Patrick Mihelich, Jiang Hu, Andrew Y. Ng
    groupTime: preference based group scheduling. [Citation Graph (0, 0)][DBLP]
    CHI, 2006, pp:1047-1056 [Conf]
  10. Jamie Pearson, Jiang Hu, Holly P. Branigan, Martin J. Pickering, Clifford Nass
    Adaptive language behavior in HCI: how expectations and beliefs about a system affect users' word choice. [Citation Graph (0, 0)][DBLP]
    CHI, 2006, pp:1177-1180 [Conf]
  11. Jiang Hu, Andi Winterboer, Clifford Nass, Johanna D. Moore, Rebecca Illowsky
    Context & usability testing: user-modeled information presentation in easy and difficult driving conditions. [Citation Graph (0, 0)][DBLP]
    CHI, 2007, pp:1343-1346 [Conf]
  12. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
    A Practical Methodology for Early Buffer and Wire Resource Allocation. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:189-194 [Conf]
  13. Jiang Hu, Sachin S. Sapatnekar
    FAR-DS: Full-Plane AWE Routing with Driver Sizing. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:84-89 [Conf]
  14. Charles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay
    Fast and flexible buffer trees that navigate the physical layout environment. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:24-29 [Conf]
  15. Ke Cao, Sorin Dobre, Jiang Hu
    Standard cell characterization considering lithography induced variations. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:801-804 [Conf]
  16. Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze
    Fast algorithms for slew constrained minimum cost buffering. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:308-313 [Conf]
  17. Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li
    Steiner network construction for timing critical nets. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:379-384 [Conf]
  18. Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu
    Navigating registers in placement for clock network minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:176-181 [Conf]
  19. Anand Rajaram, Jiang Hu, Rabi N. Mahapatra
    Reducing clock skew variability via cross links. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:18-23 [Conf]
  20. Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif
    Congestion-driven codesign of power and signal networks. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:64-69 [Conf]
  21. Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
    Path based buffer insertion. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:509-514 [Conf]
  22. Min-Seok Kim, Jiang Hu
    Associative skew clock routing for difficult instances. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:762-767 [Conf]
  23. Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C. N. Sze
    Integrated placement and skew optimization for rotary clocking. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:756-761 [Conf]
  24. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze
    Accurate estimation of global buffer delay within a floorplan. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:706-711 [Conf]
  25. Jiang Hu, Sachin S. Sapatnekar
    A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:99-103 [Conf]
  26. Anand Rajaram, Bing Lu, Wei Guo, Rabi N. Mahapatra, Jiang Hu
    Analytical Bound for Unwanted Clock Skew due to Wire Width Variation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:401-407 [Conf]
  27. V. Seth, Min Zhao, Jiang Hu
    Exploiting level sensitive latches in wire pipelining. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:283-290 [Conf]
  28. Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert
    Practical techniques to reduce skew and its variations in buffered clock networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:592-596 [Conf]
  29. Di Wu, Ganesh Venkataraman, Jiang Hu, Quiyang Li, Rabi N. Mahapatra
    DiCER: distributed and cost-effective redundancy for variation tolerance. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:393-397 [Conf]
  30. Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen
    Fast decap allocation based on algebraic multigrid. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:107-111 [Conf]
  31. Ganesh Venkataraman, Zhuo Feng, Jiang Hu, Peng Li
    Combinatorial algorithms for fast clock mesh optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:563-567 [Conf]
  32. Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li, Weiping Shi
    A new RLC buffer insertion algorithm. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:553-557 [Conf]
  33. Rupak Samanta, Ganesh Venkataraman, Jiang Hu
    Clock buffer polarity assignment for power noise reduction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:558-562 [Conf]
  34. Jiang Hu, Sachin S. Sapatnekar
    Performance Driven Global Routing Through Gradual Refinement. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:481-483 [Conf]
  35. Rishi Chaturvedi, Jiang Hu
    A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:282-0 [Conf]
  36. Jiang Hu, Mike Brzozowski
    Preference-Based Group Scheduling. [Citation Graph (0, 0)][DBLP]
    INTERACT, 2005, pp:990-993 [Conf]
  37. QianYing Wang, Clifford Nass, Jiang Hu
    Natural Language Query vs. Keyword Search: Effects of Task Complexity on Search Performance, Participant Perceptions, and Preferences. [Citation Graph (0, 0)][DBLP]
    INTERACT, 2005, pp:106-116 [Conf]
  38. Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar
    Steiner tree optimization for buffers. Blockages and bays. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:399-402 [Conf]
  39. Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
    Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:104-109 [Conf]
  40. Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay
    Porosity aware buffered steiner tree construction. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:158-165 [Conf]
  41. Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia
    Buffered Steiner trees for difficult instances. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:4-9 [Conf]
  42. Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham
    Buffer insertion with adaptive blockage avoidance. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:92-97 [Conf]
  43. Jiang Hu, Sachin S. Sapatnekar
    Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:133-138 [Conf]
  44. Anand Rajaram, David Z. Pan, Jiang Hu
    Improved algorithms for link-based non-tree clock networks for skew variability reduction. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:55-62 [Conf]
  45. Bing Lu, Jiang Hu, Gary Ellis, Haihua Su
    Process variation aware clock tree routing. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:174-181 [Conf]
  46. Bor-Yiing Su, Yao-Wen Chang, Jiang Hu
    An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:56-63 [Conf]
  47. Uday Padmanabhan, Janet Meiling Wang, Jiang Hu
    Statistical clock tree routing for robustness to process variations. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:149-156 [Conf]
  48. Di Wu, Jiang Hu, Rabi N. Mahapatra
    Coupling aware timing optimization and antenna avoidance in layer assignment. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:20-27 [Conf]
  49. Rishi Chaturvedi, Jiang Hu
    Buffered Clock Tree for High Quality IC Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:381-386 [Conf]
  50. Zhuo Feng, Peng Li, Jiang Hu
    Efficient Model Update for General Link-Insertion Networks. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:43-50 [Conf]
  51. Cheng Zhuo, Jiang Hu, Kangsheng Chen
    An Improved AMG-based Method for Fast Power Grid Analysis. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:290-295 [Conf]
  52. Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu
    Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:299-304 [Conf]
  53. Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Weiping Shi
    An Efficient Algorithm for RLC Buffer Insertion. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:171-175 [Conf]
  54. Yang Liu, Tong Zhang, Jiang Hu
    Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:749-754 [Conf]
  55. Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
    Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:383-388 [Conf]
  56. QianYing Wang, Jiang Hu, Clifford Nass
    Natural Language Interface Put in Perspective: Interaction of Search Method and Task Complexity. [Citation Graph (0, 0)][DBLP]
    NLUCS, 2005, pp:3-12 [Conf]
  57. Ganesh Venkataraman, Jiang Hu
    A Placement Methodology for Robust Clocking. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:881-886 [Conf]
  58. Jiang Hu, Sachin S. Sapatnekar
    A survey on multi-net global routing for integrated circuits. [Citation Graph (0, 0)][DBLP]
    Integration, 2001, v:31, n:1, pp:1-49 [Journal]
  59. Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
    Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:136-141 [Journal]
  60. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze
    Accurate estimation of global buffer delay within a floorplan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1140-1145 [Journal]
  61. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
    A practical methodology for early buffer and wire resource allocation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:573-583 [Journal]
  62. Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze
    Porosity-aware buffered Steiner tree construction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:517-526 [Journal]
  63. Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar
    Steiner tree optimization for buffers, blockages, and bays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:4, pp:556-562 [Journal]
  64. Jiang Hu, Sachin S. Sapatnekar
    Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:4, pp:446-458 [Journal]
  65. Jiang Hu, Sachin S. Sapatnekar
    A timing-constrained simultaneous global routing algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1025-1036 [Journal]
  66. Huibo Hou, Jiang Hu, Sachin S. Sapatnekar
    Non-Hanan routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:436-444 [Journal]
  67. Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham
    Buffer insertion with adaptive blockage avoidance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:492-498 [Journal]
  68. Anand Rajaram, Jiang Hu, Rabi N. Mahapatra
    Reducing clock skew variability via crosslinks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1176-1182 [Journal]
  69. Anand Rajaram, Bing Lu, Jiang Hu, Rabi N. Mahapatra, Wei Guo
    Analytical bound for unwanted clock skew due to wire width variation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1869-1876 [Journal]
  70. Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif
    A methodology for the simultaneous design of supply and signal networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1614-1624 [Journal]
  71. Di Wu, Jiang Hu, Rabi N. Mahapatra
    Antenna Avoidance in Layer Assignment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:4, pp:734-738 [Journal]
  72. Rishi Chaturvedi, Jiang Hu
    An efficient merging scheme for prescribed skew clock routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:750-754 [Journal]
  73. Shiyan Hu, Mahesh Ketkar, Jiang Hu
    Gate Sizing For Cell Library-Based Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:847-852 [Conf]
  74. Weixiang Shen, Yici Cai, Jiang Hu, Xianlong Hong, Bing Lu
    High performance clock routing in X-architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  75. Shiyan Hu, Jiang Hu
    Pattern sensitive placement for manufacturability. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:27-34 [Conf]
  76. Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li
    Utilizing Redundancy for Timing Critical Interconnect. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1067-1080 [Journal]
  77. Ganesh Venkataraman, Jiang Hu, Frank Liu
    Integrated Placement and Skew Optimization for Rotary Clocking. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:149-158 [Journal]

  78. A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield. [Citation Graph (, )][DBLP]


  79. Handling partial correlations in yield prediction. [Citation Graph (, )][DBLP]


  80. Low power clock buffer planning methodology in F-D placement for large scale circuit design. [Citation Graph (, )][DBLP]


  81. GPU-based parallelization for fast circuit optimization. [Citation Graph (, )][DBLP]


  82. Detecting tangled logic structures in VLSI netlists. [Citation Graph (, )][DBLP]


  83. SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal. [Citation Graph (, )][DBLP]


  84. Built-In Proactive Tuning System for Circuit Aging Resilience. [Citation Graph (, )][DBLP]


  85. Impact of lithography-friendly circuit layout. [Citation Graph (, )][DBLP]


  86. Unified adaptivity optimization of clock and logic signals. [Citation Graph (, )][DBLP]


  87. Modeling, optimization and control of rotary traveling-wave oscillator. [Citation Graph (, )][DBLP]


  88. Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding. [Citation Graph (, )][DBLP]


  89. Delay-optimal simultaneous technology mapping and placement with applications to timing optimization. [Citation Graph (, )][DBLP]


  90. Gate planning during placement for gated clock network. [Citation Graph (, )][DBLP]


  91. Discrete buffer and wire sizing for link-based non-tree clock networks. [Citation Graph (, )][DBLP]


  92. Activity and register placement aware gated clock network design. [Citation Graph (, )][DBLP]


  93. Multi-scenario buffer insertion in multi-core processor designs. [Citation Graph (, )][DBLP]


  94. A new algorithm for simultaneous gate sizing and threshold voltage assignment. [Citation Graph (, )][DBLP]


  95. Accurate clock mesh sizing via sequential quadraticprogramming. [Citation Graph (, )][DBLP]


  96. Elastic Timing Scheme for Energy-Efficient and Robust Performance. [Citation Graph (, )][DBLP]


  97. Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding. [Citation Graph (, )][DBLP]


  98. Useful clock skew optimization under a multi-corner multi-mode design framework. [Citation Graph (, )][DBLP]


  99. A dual-level adaptive supply voltage system for variation resilience. [Citation Graph (, )][DBLP]


  100. Low Power Trellis Decoder with Overscaled Supply Voltage. [Citation Graph (, )][DBLP]


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