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Yiyu Shi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hong, Xiaodong Hu, Guiying Yan
    DraXRouter: global routing in X-Architecture with dynamic resource assignment. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:618-623 [Conf]
  2. Yiyu Shi, Tong Jing, Lei He, Zhe Feng 0002, Xianlong Hong
    CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:630-635 [Conf]
  3. Hao Yu, Yiyu Shi, Lei He
    Fast analysis of structured power grid by triangularization based structure preserving model order reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:205-210 [Conf]
  4. Yiyu Shi, Paul Mesa, Hao Yu, Lei He
    Circuit simulation based obstacle-aware Steiner routing. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:385-388 [Conf]
  5. Hao Yu, Yiyu Shi, Lei He, David Smart
    A fast block structure preserving model order reduction for inverse inductance circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:7-12 [Conf]
  6. Hao Yu, Yiyu Shi, Lei He, Tanay Karnik
    Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:156-161 [Conf]
  7. Yiyu Shi, Hao Yu, Lei He
    SAMSON: a generalized second-order arnoldi method for reducing multiple source linear network with susceptance. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:25-32 [Conf]
  8. Yiyu Shi, Lei He
    Empire: an efficient and compact multiple-parameterized model order reduction method. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:51-58 [Conf]
  9. Yiyu Shi, Paul Mesa, Hao Yu, Lei He
    Circuit-simulated obstacle-aware Steiner routing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal]

  10. Incremental and on-demand random walk for iterative power distribution network analysis. [Citation Graph (, )][DBLP]


  11. Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction. [Citation Graph (, )][DBLP]


  12. Statistical multilayer process space coverage for at-speed test. [Citation Graph (, )][DBLP]


  13. A universal state-of-charge algorithm for batteries. [Citation Graph (, )][DBLP]


  14. QuickYield: an efficient global-search based parametric yield estimation with performance constraints. [Citation Graph (, )][DBLP]


  15. Efficient decoupling capacitance budgeting considering operation and process variations. [Citation Graph (, )][DBLP]


  16. Joint design-time and post-silicon optimization for digitally tuned analog circuits. [Citation Graph (, )][DBLP]


  17. Pre-ATPG path selection for near optimal post-ATPG process space coverage. [Citation Graph (, )][DBLP]


  18. Temperature-aware clock tree synthesis considering spatiotemporal hot spot correlations. [Citation Graph (, )][DBLP]


  19. Worst case timing jitter and amplitude noise in differential signaling. [Citation Graph (, )][DBLP]


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