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D. M. H. Walker: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Wanlin Cao, D. M. H. Walker, Rajarshi Mukherjee
    An efficient solution to the storage correspondence problem for large sequential circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:181-186 [Conf]
  2. Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
    Longest path selection for delay test under process variation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:98-103 [Conf]
  3. Lan Zhao, D. M. H. Walker, Fabrizio Lombardi
    IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:375-0 [Conf]
  4. D. M. H. Walker, Chris S. Kellen, Andrzej J. Strojwas
    A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor and Statistical Simulator. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:579-584 [Conf]
  5. Lei Wu, D. M. H. Walker
    A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:178-186 [Conf]
  6. Abhijit Prasad, D. M. H. Walker
    Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current Sensors. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:140-0 [Conf]
  7. Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, Weiping Shi
    CodSim -- A Combined Delay Fault Simulator. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:79-0 [Conf]
  8. Sagar S. Sabade, D. M. H. Walker
    Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:381-389 [Conf]
  9. Sagar S. Sabade, D. M. H. Walker
    CROWNE: Current Ratio Outliers with Neighbor Estimator. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:132-139 [Conf]
  10. Vijay R. Sar-Dessai, D. M. H. Walker
    Accurate Fault Modeling and Fault Simulation of Resistive Bridges. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:102-107 [Conf]
  11. Lan Zhao, D. M. H. Walker, Fabrizio Lombardi
    Bridging Fault Detection in FPGA Interconnects Using IDDQ. [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:95-104 [Conf]
  12. Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
    PARADE: PARAmetric Delay Evaluation under Process Variation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:276-280 [Conf]
  13. Hoki Kim, D. M. H. Walker, David Colby
    A practical built-in current sensor for I_DDQ testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:405-414 [Conf]
  14. Young-Jun Kwon, D. M. H. Walker
    Yiel Learning via Functional Test Data. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:626-635 [Conf]
  15. G. M. Luong, D. M. H. Walker
    Test Generation for Global Delay Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:433-442 [Conf]
  16. Yuyun Liao, D. M. H. Walker
    Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:767-775 [Conf]
  17. Wangqi Qiu, D. M. H. Walker
    An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:592-601 [Conf]
  18. Wangqi Qiu, Jing Wang, D. M. H. Walker, Divya Reddy, Zhuo Li, Weiping Shi, Hari Balachandran
    K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:223-231 [Conf]
  19. V. Ramakrishnan, D. M. H. Walker
    IC Performance Prediction System. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:336-344 [Conf]
  20. Sagar S. Sabade, D. M. H. Walker
    Improved wafer-level spatial analysis for I_DDQ limit setting. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:82-91 [Conf]
  21. Vijay R. Sar-Dessai, D. M. H. Walker
    Resistive bridge fault modeling, simulation and test generation. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:596-605 [Conf]
  22. Zoran Stanojevic, Hari Balachandran, D. M. H. Walker, Fred Lakbani, Jayashree Saxena, Kenneth M. Butler
    Computer-aided fault to defect mapping (CAFDM) for defect diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:729-738 [Conf]
  23. Zoran Stanojevic, D. M. H. Walker
    FedEx - a fast bridging fault extractor. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:696-703 [Conf]
  24. D. M. H. Walker
    Design for Yield and Reliability is MORE Important Than DFT. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1146- [Conf]
  25. Lan Zhao, D. M. H. Walker, Fabrizio Lombardi
    Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:1037-0 [Conf]
  26. Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
    A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:97-102 [Conf]
  27. Wangqi Qiu, D. M. H. Walker
    Testing the Path Delay Faults of ISCAS85 Circuit c6288. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:19-0 [Conf]
  28. Bin Xue, D. M. H. Walker
    Is IDDQ Test of Microprocessors Feasible? [Citation Graph (0, 0)][DBLP]
    MTV, 2005, pp:63-69 [Conf]
  29. Hyun Sung Kim, D. M. H. Walker
    Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in {VLSI} Circuits. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:76-82 [Conf]
  30. Sagar S. Sabade, D. M. H. Walker
    Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:755-760 [Conf]
  31. Sagar S. Sabade, D. M. H. Walker
    Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:361-0 [Conf]
  32. Sagar S. Sabade, D. M. H. Walker
    Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:889-894 [Conf]
  33. Hari Balachandran, D. M. H. Walker
    Improvement of SRAM-based failure analysis using calibrated Iddq testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:130-137 [Conf]
  34. Byungwoo Choi, D. M. H. Walker
    Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:49-54 [Conf]
  35. Chul Young Lee, D. M. H. Walker
    PROBE: A PPSFP Simulator for Resistive Bridging Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:105-112 [Conf]
  36. Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker
    A Circuit Level Fault Model for Resistive Opens and Bridges. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:379-384 [Conf]
  37. Yuyun Liao, D. M. H. Walker
    Optimal voltage testing for physically-based faults. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:344-353 [Conf]
  38. Wangqi Qiu, Xiang Lu, Jing Wang, Zhuo Li, D. M. H. Walker, Weiping Shi
    A Statistical Fault Coverage Metric for Realistic Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:37-42 [Conf]
  39. Debashis Nayak, D. M. H. Walker
    Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:70-79 [Conf]
  40. Sagar S. Sabade, D. M. H. Walker
    Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:81-86 [Conf]
  41. Sagar S. Sabade, D. M. H. Walker
    Use of Multiple IDDQ Test Metrics for Outlier Identification. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:31-38 [Conf]
  42. Sagar S. Sabade, D. M. H. Walker
    On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:65-72 [Conf]
  43. Jing Wang, Xiang Lu, Wangqi Qiu, Ziding Yue, Steve Fancler, Weiping Shi, D. M. H. Walker
    Static Compaction of Delay Tests Considering Power Supply Noise. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:235-240 [Conf]
  44. Sagar S. Sabade, D. M. H. Walker
    IDDQ Test: Will It Survive the DSM Challenge? [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:8-16 [Journal]
  45. Sagar S. Sabade, D. M. H. Walker
    IDDQ data analysis using neighbor current ratios. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2004, v:50, n:5, pp:287-294 [Journal]
  46. Lan Zhao, D. M. H. Walker, Fabrizio Lombardi
    IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:10, pp:1136-1152 [Journal]
  47. Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
    Longest-path selection for delay test under process variation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1924-1929 [Journal]
  48. D. M. H. Walker, Stephen W. Director
    VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:541-556 [Journal]
  49. D. M. H. Walker, Chris S. Kellen, David M. Svoboda, Andrzej J. Strojwas
    The CDB/HCDB semiconductor wafer representation server. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:283-295 [Journal]
  50. Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker
    A circuit level fault model for resistive bridges. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:546-559 [Journal]
  51. Sagar S. Sabade, D. M. H. Walker
    IDDX-based test methods: A survey. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:2, pp:159-198 [Journal]
  52. Sagar S. Sabade, D. M. H. Walker
    Estimation of fault-free leakage current using wafer-level spatial information. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:91-94 [Journal]

  53. Challenges in Delay Testing of Integrated Circuits. [Citation Graph (, )][DBLP]


  54. Dynamic Compaction for High Quality Delay Test. [Citation Graph (, )][DBLP]


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