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Eduard Cerny: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Eduard Cerny, Ashvin Dsouza, Kevin Harer, Pei-Hsin Ho, Hi-Keung Tony Ma
    Supporting sequential assumptions in hybrid verification. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1035-1038 [Conf]
  2. K. D. Anon, N. Boulerice, Eduard Cerny, Francisco Corella, Michel Langevin, Xiaoyu Song, Sofiène Tahar, Ying Xu, Zijian Zhou
    MDG Tools for the Verification of RTL Designs. [Citation Graph (0, 0)][DBLP]
    CAV, 1996, pp:433-436 [Conf]
  3. Michel Langevin, Eduard Cerny
    Comparing Generic State Machines. [Citation Graph (0, 0)][DBLP]
    CAV, 1991, pp:466-476 [Conf]
  4. Ying Xu, Eduard Cerny, Xiaoyu Song, Francisco Corella, Otmane Aït Mohamed
    Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs. [Citation Graph (0, 0)][DBLP]
    CAV, 1998, pp:219-231 [Conf]
  5. Otmane Aït Mohamed, Xiaoyu Song, Eduard Cerny
    On the non-termination of MDGs-based abstract state enumeration. [Citation Graph (0, 0)][DBLP]
    CHARME, 1997, pp:218-235 [Conf]
  6. Francisco Corella, Michel Langevin, Eduard Cerny, Zijian Zhou, Xiaoyu Song
    State enumeration with abstract descriptions of state machines. [Citation Graph (0, 0)][DBLP]
    CHARME, 1995, pp:146-160 [Conf]
  7. Ying Xu, Eduard Cerny, Allan Silburt, A. Coady, Ying Liu, Philip Pownall
    Practical Application of Formal Verification Techniques on a Frame Mux/Demux Chip from Nortel Semiconductors. [Citation Graph (0, 0)][DBLP]
    CHARME, 1999, pp:110-124 [Conf]
  8. Karim Khordoc, Mario Dufresne, Eduard Cerny, P. A. Babkine, Allan Silburt
    Integrating Behavior and Timing in Executable Specifications. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:399-416 [Conf]
  9. Pierre Girodias, Eduard Cerny, William J. Older
    Solving Linear, Min and Max Constraint Systems Using CLP based on Relational Interval Arithmetic. [Citation Graph (0, 0)][DBLP]
    CP, 1995, pp:186-203 [Conf]
  10. L.-P. Demers, P. Jacques, S. Fauvel, Eduard Cerny
    CHESHIRE: An Object-Oriented Integration of VLSI CAD Tools. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:750-756 [Conf]
  11. C. Roy, L.-P. Demers, Eduard Cerny, Jan Gecsei
    An object-oriented swicth-level simulator. [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:623-629 [Conf]
  12. Michel Langevin, Eduard Cerny, Jörg Wilberg, Heinrich Theodor Vierhaus
    Local microcode generation in system design. [Citation Graph (0, 0)][DBLP]
    Code Generation for Embedded Processors, 1994, pp:171-187 [Conf]
  13. Maroun Kassab, Eduard Cerny, Sidi Aourid, Thomas H. Krodel
    Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:796-802 [Conf]
  14. Michel Langevin, Eduard Cerny
    An Extended OBDD Representation for Extended FSMs. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:208-213 [Conf]
  15. Eduard Cerny, Fen Jin
    Verification of Real Time Controllers Against Timing Diagram Specifications Using Constraint Logic Programming. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10229-10236 [Conf]
  16. Eduard Cerny, Francisco Corella, Michel Langevin, Xiaoyu Song, Sofiène Tahar, Zijian Zhou
    Verification with Abstract State Machines Using MDGs. [Citation Graph (0, 0)][DBLP]
    Formal Hardware Verification, 1997, pp:79-113 [Conf]
  17. Jin Hou, Eduard Cerny
    Model Reductions and a Case Study. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:299-315 [Conf]
  18. Fen Jin, Henrik Hulgaard, Eduard Cerny
    Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1998, pp:167-184 [Conf]
  19. Zijian Zhou, Xiaoyu Song, Sofiène Tahar, Eduard Cerny, Francisco Corella, Michel Langevin
    Formal Verification of the Island Tunnel Controller Using Multiway Decision Graphs. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:233-247 [Conf]
  20. Yi Feng, Eduard Cerny
    Term ordering problem on MDG. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:160-165 [Conf]
  21. Otmane Aït Mohamed, Eduard Cerny, Xiaoyu Song
    MDG-based Verification by Retiming and Combinational Transformations. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:356-361 [Conf]
  22. Sofiène Tahar, Zijian Zhou, Xiaoyu Song, Eduard Cerny, Michel Langevin
    Formal Verification of an ATM Switch Fabric using Multiway Decision Graphs. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:106-111 [Conf]
  23. Zijian Zhou, Xiaoyu Song, Francisco Corella, Eduard Cerny, Michel Langevin
    Partitioning transition relations efficiently and automatically. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:106-111 [Conf]
  24. Eduard Cerny, C. Mauras
    Tautology Checking Using Cross-Controllability and Cross-Observability Relations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:34-37 [Conf]
  25. Karim Khordoc, Mario Dufresne, Eduard Cerny
    A Stimulus/Response System Based on Hierarchical Timing Diagrams. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:358-361 [Conf]
  26. Eduard Cerny
    A Compositional Transformation for Formal Verification. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:240-244 [Conf]
  27. Eduard Cerny
    Verification of I/O Trace Set Inclusion for a Class of Non-Deterministic Finite State Machines. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:526-530 [Conf]
  28. Eduard Cerny, Fen Jin
    Verification of Real Time Controllers Against Timing Diagram Specifications Using Constraint Logic Programming. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:32-39 [Conf]
  29. Michel Langevin, Eduard Cerny
    A Recursive Technique for Computing Lower-Bound Performance of Schedules. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:16-20 [Conf]
  30. Michel Langevin, Sofiène Tahar, Zijian Zhou, Xiaoyu Song, Eduard Cerny
    Behavioral Verification of an ATM Switch Fabric using Implicit Abstract State Enumeration. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:20-26 [Conf]
  31. Karim Khordoc, Eduard Cerny
    Modeling Cell Processing Hardware with Action Diagrams. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:245-248 [Conf]
  32. E. K. Ogoubi, Eduard Cerny
    Synthesis of checker EFSMs from timing diagram specifications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:13-18 [Conf]
  33. Yi Feng, Eduard Cerny
    Variable ordering on multiway decision graphs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:337-340 [Conf]
  34. Gregor von Bochmann, Eduard Cerny, G. Gerber, Rachida Dssouli, Michel Maksud, B. H. Phan, Behçet Sarikaya, Jean-Marc Serre
    Use of Formal Specifications for Protocol Design, Implementation and Testing. [Citation Graph (0, 0)][DBLP]
    PSTV, 1984, pp:137-144 [Conf]
  35. Gregor von Bochmann, Eduard Cerny, Michel Gagne, Claude Jard, Alain Léveillé, Clement Lacaille, Michel Maksud, K. S. Raghunathan, Behçet Sarikaya
    Some Experience with the Use of Formal Specifications. [Citation Graph (0, 0)][DBLP]
    PSTV, 1982, pp:171-185 [Conf]
  36. Abdessatar Abderrahman, Eduard Cerny, Bozena Kaminska
    CLP-based Multifrequency Test Generation for Analog Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:158-165 [Conf]
  37. Mohamed Meknassi, El Mostapha Aboulhamid, Eduard Cerny
    Algorithm for the graph-partitioning problem using a problem transformation method. [Citation Graph (0, 0)][DBLP]
    Computer-Aided Design, 1992, v:24, n:7, pp:397-398 [Journal]
  38. Eduard Cerny
    Some issues in protocol implementation testing. [Citation Graph (0, 0)][DBLP]
    Computer Communication Review, 1984, v:14, n:2, pp:259-260 [Journal]
  39. Ying Xu, Xiaoyu Song, Eduard Cerny, Otmane Aït Mohamed
    Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs (MDGs). [Citation Graph (0, 0)][DBLP]
    Comput. J., 2004, v:47, n:1, pp:71-84 [Journal]
  40. Sophie Renault, Eduard Cerny
    Improving Termination of MDG-Based Abstract State Enumeration via Term Schematization. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 1999, v:23, n:2, pp:- [Journal]
  41. Francisco Corella, Zijian Zhou, Xiaoyu Song, Michel Langevin, Eduard Cerny
    Multiway Decision Graphs for Automated Hardware Verification. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1997, v:10, n:1, pp:7-46 [Journal]
  42. Otmane Aït Mohamed, Xiaoyu Song, Eduard Cerny, Sofiène Tahar, Zijian Zhou
    MDG-Based State Enumeration By Retiming And Circuit Transformation. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2004, v:13, n:5, pp:1111-1132 [Journal]
  43. Jocelyn Cloutier, Eduard Cerny, F. Guertin
    Model partitioning and the performance of distributed timewarp simulation of logic circuits. [Citation Graph (0, 0)][DBLP]
    Simul. Pr. Theory, 1997, v:5, n:1, pp:83-99 [Journal]
  44. El Mostapha Aboulhamid, Eduard Cerny
    A Class of Test Generators for Built-In Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:10, pp:957-959 [Journal]
  45. El Mostapha Aboulhamid, Eduard Cerny
    Built-In Testing of One-Dimensional Unilateral Iterative Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:6, pp:560-564 [Journal]
  46. Christian Berthet, Eduard Cerny
    An Algebraic Model for Asynchronous Circuits Verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:7, pp:835-847 [Journal]
  47. Eduard Cerny
    Comments on ``Equational Logic''. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1976, v:25, n:1, pp:102-103 [Journal]
  48. Eduard Cerny
    Controllability and Fault Observability in Modular Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:10, pp:896-903 [Journal]
  49. Eduard Cerny, Jan Gecsei
    Functional Description of Connector-Switch-Attenuator Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:1, pp:111-114 [Journal]
  50. Eduard Cerny, Miguel A. Marin
    An Approach to Unified Methodology of Combinational Switching Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1977, v:26, n:8, pp:745-756 [Journal]
  51. Eduard Cerny, Daniel Mange, Eduardo Sanchez
    Synthesis of Minimal Binary Decision Trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:7, pp:472-482 [Journal]
  52. Jan Gecsei, Eduard Cerny
    Self-Adjusting Networks for VLSI Simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:9, pp:1114-1120 [Journal]
  53. Younès Karkouri, El Mostapha Aboulhamid, Eduard Cerny, Alain Verreault
    Use of Fault Dropping for Multiple Fault Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:1, pp:98-103 [Journal]
  54. Jianli Sun, Eduard Cerny, Jan Gecsei
    Fault Tolerance in a Class of Sorting Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:7, pp:827-837 [Journal]
  55. Abdessatar Abderrahman, Eduard Cerny, Bozena Kaminska
    Worst case tolerance analysis and CLP-based multifrequency test generation for analog circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:3, pp:332-345 [Journal]
  56. Guy Bois, Eduard Cerny
    Efficient generation of diagonal constraints for 2-D mask compaction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1119-1126 [Journal]
  57. Samir Boubezari, Eduard Cerny, Bozena Kaminska, Benoit Nadeau-Dostie
    Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1327-1340 [Journal]
  58. Jean Paul Caisso, Eduard Cerny, Nicholas C. Rumin
    A recursive technique for computing delays in series-parallel MOS transistor circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:589-595 [Journal]
  59. Eduard Cerny, Jan Gecsei
    Simulation of MOS Circuits by Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:4, pp:685-693 [Journal]
  60. Eduard Cerny, John P. Hayes, Nicholas C. Rumin
    Accuracy of magnitude-class calculations in switch-level modeling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:4, pp:443-452 [Journal]
  61. Sofiène Tahar, Xiaoyu Song, Eduard Cerny, Zijian Zhou, Michel Langevin, Otmane Aït Mohamed
    Modeling and formal verification of the Fairisle ATM switch fabricusing MDGs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:956-972 [Journal]
  62. Pierre Girodias, Eduard Cerny, William J. Older
    Solving Linear, Min and Max Constraint Systems Using CLP Based on Relational Interval Arithmetic. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 1997, v:173, n:1, pp:253-281 [Journal]
  63. Otmane Aït Mohamed, Xiaoyu Song, Eduard Cerny
    On the non-termination of M-based abstract state enumeration. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 2003, v:300, n:1-3, pp:161-179 [Journal]
  64. Karim Khordoc, Eduard Cerny
    Semantics and verification of action diagrams with linear timing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:1, pp:21-50 [Journal]
  65. Michel Langevin, Eduard Cerny
    A recursive technique for computing lower-bound performance of schedules. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1996, v:1, n:4, pp:443-455 [Journal]
  66. Behçet Sarikaya, Gregor von Bochmann, Eduard Cerny
    A Test Design Methodology for Protocol Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1987, v:13, n:5, pp:518-531 [Journal]

  67. Interface timing verification with delay correlation using constraint logic programming. [Citation Graph (, )][DBLP]


  68. Gate-level timing verification using waveform narrowing. [Citation Graph (, )][DBLP]


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