The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Massimo Bombana: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alberto Allara, Massimo Bombana, Patrizia Cavalloro, Wolfgang Nebel, Wolfram Putzke-Röming, Martin Radetzki
    ATM Cell Modelling using Objective VHDL. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:261-264 [Conf]
  2. Massimo Bombana, Patrizia Cavalloro, Salvatore Conigliaro, Roger B. Hughes, Gerry Musgrave, Giuseppe Zaza
    Design-Flow and Synthesis for ASICs: A Case Study. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:292-297 [Conf]
  3. Francesco Bruschi, Massimo Bombana
    A Design Methodology for the Exploitation of High Level Communication Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:180-185 [Conf]
  4. Massimo Bombana, Francesco Bruschi
    SystemC-VHDL Co-Simulation and Synthesis in the HW Domain. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:20101-20105 [Conf]
  5. Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza
    Reduction of Fault Detection Costs through Testable Design of Sequential Architectures with Signal Feedbacks. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:223-230 [Conf]
  6. Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza
    An Expert Solution to Functional Testability Analysis of VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    SEKE, 1993, pp:263-265 [Conf]
  7. G. Bezzi, Massimo Bombana, Patrizia Cavalloro, Salvatore Conigliaro, Giuseppe Zaza
    Quantitative Evaluation of Formal Based Synthesis in ASIC Design. [Citation Graph (0, 0)][DBLP]
    TPCD, 1994, pp:286-291 [Conf]
  8. Massimo Bombana, Patrizia Cavalloro, Giuseppe Zaza
    Specification and Formal Synthesis of Digital Circuits. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1992, pp:475-484 [Conf]
  9. Alberto Allara, Massimo Bombana, William Fornaciari, Fabio Salice
    A Case Study in Design Space Exploration: The Tosca Environment Applied to a Telecommunication Link Controller. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:60-72 [Journal]
  10. Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza
    ALADIN: a multilevel testability analyzer for VLSI system design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:157-171 [Journal]

Search in 0.002secs, Finished in 0.003secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002