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Massimo Bombana:
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- Alberto Allara, Massimo Bombana, Patrizia Cavalloro, Wolfgang Nebel, Wolfram Putzke-Röming, Martin Radetzki
ATM Cell Modelling using Objective VHDL. [Citation Graph (0, 0)][DBLP] ASP-DAC, 1998, pp:261-264 [Conf]
- Massimo Bombana, Patrizia Cavalloro, Salvatore Conigliaro, Roger B. Hughes, Gerry Musgrave, Giuseppe Zaza
Design-Flow and Synthesis for ASICs: A Case Study. [Citation Graph (0, 0)][DBLP] DAC, 1995, pp:292-297 [Conf]
- Francesco Bruschi, Massimo Bombana
A Design Methodology for the Exploitation of High Level Communication Synthesis. [Citation Graph (0, 0)][DBLP] DATE, 2004, pp:180-185 [Conf]
- Massimo Bombana, Francesco Bruschi
SystemC-VHDL Co-Simulation and Synthesis in the HW Domain. [Citation Graph (0, 0)][DBLP] DATE, 2003, pp:20101-20105 [Conf]
- Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza
Reduction of Fault Detection Costs through Testable Design of Sequential Architectures with Signal Feedbacks. [Citation Graph (0, 0)][DBLP] DFT, 1993, pp:223-230 [Conf]
- Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza
An Expert Solution to Functional Testability Analysis of VLSI Circuits. [Citation Graph (0, 0)][DBLP] SEKE, 1993, pp:263-265 [Conf]
- G. Bezzi, Massimo Bombana, Patrizia Cavalloro, Salvatore Conigliaro, Giuseppe Zaza
Quantitative Evaluation of Formal Based Synthesis in ASIC Design. [Citation Graph (0, 0)][DBLP] TPCD, 1994, pp:286-291 [Conf]
- Massimo Bombana, Patrizia Cavalloro, Giuseppe Zaza
Specification and Formal Synthesis of Digital Circuits. [Citation Graph (0, 0)][DBLP] TPHOLs, 1992, pp:475-484 [Conf]
- Alberto Allara, Massimo Bombana, William Fornaciari, Fabio Salice
A Case Study in Design Space Exploration: The Tosca Environment Applied to a Telecommunication Link Controller. [Citation Graph (0, 0)][DBLP] IEEE Design & Test of Computers, 2000, v:17, n:2, pp:60-72 [Journal]
- Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza
ALADIN: a multilevel testability analyzer for VLSI system design. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:157-171 [Journal]
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