The SCEAS System
Navigation Menu

Search the dblp DataBase


Martin Radetzki: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alberto Allara, Massimo Bombana, Patrizia Cavalloro, Wolfgang Nebel, Wolfram Putzke-Röming, Martin Radetzki
    ATM Cell Modelling using Objective VHDL. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:261-264 [Conf]
  2. Wolfram Putzke-Röming, Martin Radetzki, Wolfgang Nebel
    A Flexible Message Passing Mechanism for Objective VHDL. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:242-249 [Conf]
  3. Martin Radetzki, Ansgar Stammermann, Wolfram Putzke-Röming, Wolfgang Nebel
    Data Type Analysis for Hardware Synthesis from Object-Oriented Models. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:491-0 [Conf]
  4. Andreas Vörg, Martin Radetzki, Wolfgang Rosenstiel
    Measurement of IP Qualification Costs and Benefits. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:996-1001 [Conf]
  5. Guido Schumacher, Bernhard Josko, Gerhard Wagner, Martin Radetzki
    Development of a Telephone Answering Machine in a Lab - FPGAs in Education. [Citation Graph (0, 0)][DBLP]
    FPL, 1996, pp:400-404 [Conf]
  6. Hans-Jürgen Brand, Steffen Rülke, Martin Radetzki
    IPQ: IP Qualification for Efficient System Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:478-482 [Conf]
  7. Ralf Seepold, Natividad Martínez Madrid, Andreas Vörg, Wolfgang Rosenstiel, Martin Radetzki, P. Neumann, J. Haase
    A Qualification Platform for Design Reuse. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:75-80 [Conf]
  8. Martin Schaaf, Andrea Freßmann, Rainer Maximini, Ralph Bergmann, Alexander Tartakovski, Martin Radetzki
    Intelligent IP retrieval driven by application requirements. [Citation Graph (0, 0)][DBLP]
    Integration, 2004, v:37, n:4, pp:253-287 [Journal]
  9. Martin Radetzki, Wolfram Putzke-Röming, Wolfgang Nebel
    A Unified Approach to Object-Oriented VHDL. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:3, pp:523-545 [Journal]
  10. Rauf Salimi Khaligh, Martin Radetzki
    Efficient and Extensible Transaction Level Modeling Based on an Object Oriented Model of Bus Transactions. [Citation Graph (0, 0)][DBLP]
    IESS, 2007, pp:313-324 [Conf]

  11. Accuracy-Adaptive Simulation of Transaction Level Models. [Citation Graph (, )][DBLP]

  12. Test exploration and validation using transaction level models. [Citation Graph (, )][DBLP]

  13. Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs. [Citation Graph (, )][DBLP]

  14. A data traffic efficient H.264 deblocking IP. [Citation Graph (, )][DBLP]

  15. Efficient Parallel Transaction Level Simulation by Exploiting Temporal Decoupling. [Citation Graph (, )][DBLP]

  16. Fault-tolerant architecture and deflection routing for degradable NoC switches. [Citation Graph (, )][DBLP]

  17. A Latency, Preemption and Data Transfer Accurate Adaptive Transaction Level Model for Efficient Simulation of Pipelined Buses. [Citation Graph (, )][DBLP]

  18. Modelling Alternatives for Cycle Approximate Bus TLMs. [Citation Graph (, )][DBLP]

  19. SystemC TLM Transaction Modelling and Dispatch for Active Object. [Citation Graph (, )][DBLP]

  20. sciPROVE: C++ Based Verification Environment for IP and SoC Design1. [Citation Graph (, )][DBLP]

Search in 0.017secs, Finished in 0.019secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002