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Title:
Author:
Taewhan Kim: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Meeyoung Cha, Chun-Gi Lyuh, Taewhan Kim
    Resource-constrained low-power bus encoding with crosstalk delay elimination. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:834-837 [Conf]
  2. Yoonseo Choi, Taewhan Kim
    Memory access driven storage assignment for variables in embedded system design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:478-481 [Conf]
  3. Youngtae Kim, Taewhan Kim
    Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:622-628 [Conf]
  4. Taewhan Kim, Junhyung Um
    A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:313-316 [Conf]
  5. Keoncheol Shin, Taewhan Kim
    An integrated approach to timing-driven synthesis and placement of arithmetic circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:155-158 [Conf]
  6. Pilok Lim, Taewhan Kim
    Thermal-aware high-level synthesis based on network flow method. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:124-129 [Conf]
  7. Yongseok Choi, Naehyuck Chang, Taewhan Kim
    DC-DC converter-aware power management for battery-operated embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:895-900 [Conf]
  8. Yoonseo Choi, Taewhan Kim
    Address assignment combined with scheduling in DSP code generation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:225-230 [Conf]
  9. Yoonseo Choi, Taewhan Kim
    Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:881-886 [Conf]
  10. Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu
    A Static Estimation Technique of Power Sensitivity in Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:215-219 [Conf]
  11. Taewhan Kim, William Jao, Steven W. K. Tjiang
    Arithmetic Optimization Using Carry-Save-Adders. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:433-438 [Conf]
  12. Jungeun Kim, Taewhan Kim
    Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:105-110 [Conf]
  13. Taewhan Kim, C. L. Liu
    Utilization of Multiport Memories in Data Path Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:298-302 [Conf]
  14. Woo-Cheol Kwon, Taewhan Kim
    Optimal voltage allocation techniques for dynamically variable voltage processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:125-130 [Conf]
  15. Chun-Gi Lyuh, Taewhan Kim
    Memory access scheduling and binding considering energy minimization in multi-bank memory systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:81-86 [Conf]
  16. Junhyung Um, Taewhan Kim
    Layout-aware synthesis of arithmetic circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:207-212 [Conf]
  17. Jaewon Seo, Taewhan Kim, Ki-Seok Chung
    Profile-based optimal intra-task voltage scheduling for hard real-time applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:87-92 [Conf]
  18. Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda
    An integrated algorithm for memory allocation and assignment in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:608-611 [Conf]
  19. Junhyung Um, Taewhan Kim, C. L. Liu
    A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:98-103 [Conf]
  20. Junhyung Um, Woo-Cheol Kwon, Sungpack Hong, Young-Taek Kim, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo, Taewhan Kim
    A systematic IP and bus subsystem modeling for platform-based system design. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:560-564 [Conf]
  21. Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu
    A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:586-590 [Conf]
  22. Ki-Seok Chung, Taewhan Kim, Chien-Liang Liu
    Behavioral-level partitioning for low power design in control-dominated application. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:156-161 [Conf]
  23. Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung
    An accurate evaluation of routing density for symmetrical FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:51-55 [Conf]
  24. Young-Jun Kim, Taewhan Kim
    HW/SW partitioning techniques for multi-mode multi-task embedded applications. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:25-30 [Conf]
  25. Keoncheol Shin, Taewhan Kim
    Leakage power minimization for the synthesis of parallel multiplier circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:166-169 [Conf]
  26. Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung
    A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:137-143 [Conf]
  27. Sungpack Hong, Taewhan Kim
    Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:312-317 [Conf]
  28. Taewhan Kim, Jane W.-S. Liu, C. L. Liu
    A Scheduling Algorithm for Conditional Resource Sharing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:84-87 [Conf]
  29. Gernot Koch, Taewhan Kim, Reiner Genevriere
    A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:33-38 [Conf]
  30. Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim
    Coupling-aware high-level interconnect synthesis for low power. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:609-613 [Conf]
  31. Chun-Gi Lyuh, Taewhan Kim, Chien-Liang Liu
    An Integrated Data Path Optimization for Low Power Based on Network Flow Method. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:553-559 [Conf]
  32. Junhyung Um, Taewhan Kim
    Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:197-200 [Conf]
  33. Jaewon Seo, Taewhan Kim, Nikil D. Dutt
    Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:450-455 [Conf]
  34. Junhyung Um, Jae-Hoon Kim, Taewhan Kim
    Layout-driven resource sharing in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:614-618 [Conf]
  35. Junhyung Um, Taewhan Kim, C. L. Liu
    Optimal allocation of carry-save-adders in arithmetic optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:410-413 [Conf]
  36. Yoonseo Choi, Taewhan Kim
    An efficient low-power binding algorithm in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:321-324 [Conf]
  37. Jaewon Seo, Taewhan Kim
    Memory exploration utilizing scheduling effects in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:73-76 [Conf]
  38. Yoonseo Choi, Taewhan Kim
    Address code optimization using code scheduling for digital signal processors. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:481-484 [Conf]
  39. Unni Narayanan, Ki-Seok Chung, Taewhan Kim
    Enhanced bus invert encodings for low-power. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:25-28 [Conf]
  40. Taewhan Kim
    Application-Driven Low-Power Techniques Using Dynamic Voltage Scaling. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2006, pp:199-206 [Conf]
  41. Sungpack Hong, Taewhan Kim
    Bus Optimization for Low Power in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2003, v:12, n:1, pp:1-18 [Journal]
  42. Sungpack Hong, Taewhan Kim, Unni Narayanan, Ki-Seok Chung
    Decomposition of Bus-Invert Coding for Low-Power I/O. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2000, v:10, n:1-2, pp:101-112 [Journal]
  43. Yoonseo Choi, Taewhan Kim
    Binding Algorithm for Power Optimization Based on Network Flow Method. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:3, pp:259-272 [Journal]
  44. Ki-Seok Chung, Taewhan Kim, C. L. Liu
    A Complete Model for Glitch Analysis in Logic Circuits. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:2, pp:137-154 [Journal]
  45. Youngtae Kim, Taewhan Kim
    An Accurate Exploration of Timing and Area Trade-Offs in Arithmetic Optimization Using Carry-Save-Adders. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2000, v:10, n:5-6, pp:279-292 [Journal]
  46. Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung
    CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:7, pp:829-842 [Journal]
  47. Junhyung Um, Taewhan Kim
    An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:3, pp:215-233 [Journal]
  48. Yoonseo Choi, Taewhan Kim
    Address assignment in DSP code generation - an integrated approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:976-984 [Journal]
  49. Yoonseo Choi, Taewhan Kim, Hwansoo Han
    Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:278-287 [Journal]
  50. Taewhan Kim, William Jao, Steven W. K. Tjiang
    Circuit optimization using carry-save-adder cells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:974-984 [Journal]
  51. Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang
    Domino logic synthesis based on implication graph. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:232-240 [Journal]
  52. Taewhan Kim, Junhyung Um
    A practical approach to the synthesis of arithmetic circuits usingcarry-save-adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:5, pp:615-624 [Journal]
  53. Taewhan Kim, Noritake Yonezawa, Jane W.-S. Liu, C. L. Liu
    A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:425-438 [Journal]
  54. Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim
    Coupling-aware high-level interconnect synthesis [IC layout]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:157-164 [Journal]
  55. Junhyung Um, Taewhan Kim
    Synthesis of arithmetic circuits considering layout effects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1487-1503 [Journal]
  56. Jaewon Seo, Taewhan Kim, Joonwon Lee
    Optimal intratask dynamic voltage-scaling technique and its practical extensions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:47-57 [Journal]
  57. Woo-Cheol Kwon, Taewhan Kim
    Optimal voltage allocation techniques for dynamically variable voltage processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2005, v:4, n:1, pp:211-230 [Journal]
  58. Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang
    Minimum delay optimization for domino circuits - a coupling-aware approach. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:2, pp:202-213 [Journal]
  59. Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu
    Logic transformation for low-power synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:2, pp:265-283 [Journal]
  60. Keoncheol Shin, Taewhan Kim
    Tight integration of timing-driven synthesis and placement of parallel multiplier circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:766-775 [Journal]
  61. Kyoung-Hwan Lim, Yonghwan Kim, Taewhan Kim
    Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:765-770 [Conf]
  62. Zhenmin Li, Taewhan Kim
    Address Code Optimization Exploiting Code Scheduling in DSP Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1573-1576 [Conf]
  63. Benjamin Carrión Schäfer, Yongho Lee, Taewhan Kim
    Temperature-Aware Compilation for VLIWProcessors. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2007, pp:426-431 [Conf]
  64. Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang
    Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:879-887 [Journal]
  65. Chun-Gi Lyuh, Taewhan Kim
    High-level synthesis for low power based on network flow method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:364-375 [Journal]
  66. Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda
    Memory allocation and mapping in high-level synthesis - an integrated approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:928-938 [Journal]
  67. Junhyung Um, Taewhan Kim
    Resource Sharing Combined with Layout Effects in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:44, n:3, pp:231-243 [Journal]
  68. Young-Jun Kim, Taewhan Kim
    A HW/SW Partitioner for Multi-Mode Multi-Task Embedded Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:44, n:3, pp:269-283 [Journal]

  69. Optimal allocation and placement of thermal sensors for reconfigurable systems and its practical extension. [Citation Graph (, )][DBLP]


  70. Timing variation-aware task scheduling and binding for MPSoC. [Citation Graph (, )][DBLP]


  71. Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization. [Citation Graph (, )][DBLP]


  72. Clock tree synthesis with pre-bond testability for 3D stacked IC designs. [Citation Graph (, )][DBLP]


  73. Timing variation-aware high-level synthesis. [Citation Graph (, )][DBLP]


  74. Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits. [Citation Graph (, )][DBLP]


  75. Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization. [Citation Graph (, )][DBLP]


  76. Power-gating-aware high-level synthesis. [Citation Graph (, )][DBLP]


  77. Clock buffer polarity assignment considering the effect of delay variations. [Citation Graph (, )][DBLP]


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