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Supratik Chakraborty: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Supratik Chakraborty, Rajeev Murgai
    Layout-driven Timing Optimization by Generalized De Morgan Transform. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:647-654 [Conf]
  2. Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan
    Functional Verification of System on Chips-Practices, Issues and Challenges. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:11-13 [Conf]
  3. Rohan Angrish, Supratik Chakraborty
    Probabilistic Timing Analysis of Asynchronous Systems with Moments of Delay. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:99-108 [Conf]
  4. Supratik Chakraborty, David L. Dill
    More Accurate Polynomial-Time Min-Max Timing Simulation. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1997, pp:112-0 [Conf]
  5. Supratik Chakraborty, David L. Dill, Kun-Yung Chang, Kenneth Y. Yun
    Timing Analysis of Extended Burst-Mode Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1997, pp:101-111 [Conf]
  6. Joycee Mekie, Supratik Chakraborty, Dinesh K. Sharma, Girish Venkataramani, P. S. Thiagarajan
    Interface Design for Rationally Clocked GALS Systems. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2006, pp:160-171 [Conf]
  7. Supratik Chakraborty, David L. Dill
    Approximate algorithms for time separation of events. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:190-194 [Conf]
  8. Dipanwita Roy Chowdhury, Supratik Chakraborty, B. Vamsi, B. Pal Chaudhuri
    Cellular automata based synthesis of easily and fully testable FSMs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:650-653 [Conf]
  9. Babita Sharma, Paritosh K. Pandya, Supratik Chakraborty
    Bounded Validity Checking of Interval Duration Logic. [Citation Graph (0, 0)][DBLP]
    TACAS, 2005, pp:301-316 [Conf]
  10. Dina Thomas, Supratik Chakraborty, Paritosh K. Pandya
    Efficient Guided Symbolic Reachability Using Reachability Expressions. [Citation Graph (0, 0)][DBLP]
    TACAS, 2006, pp:120-134 [Conf]
  11. Supratik Chakraborty, Rajeev Murgai
    Complexity Of Minimum-Delay Gate Resizing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:425-430 [Conf]
  12. Supratik Chakraborty, Rajeev Murgai
    Layout-Driven Timing Optimization by Generalized De Morgan Transform. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:647-654 [Conf]
  13. Dipanwita Roy Chowdhury, Supratik Chakraborty, Parimal Pal Chaudhuri
    Synthesis of Self-Checking Sequential Machines Using Cellular Automata. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:107- [Conf]
  14. Joycee Mekie, Supratik Chakraborty, Dinesh K. Sharma
    Evaluation of pausible clocking for interfacing high speed IP cores in GALS Framework. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:559-564 [Conf]
  15. S. Nandi, Vamsi Boppana, Supratik Chakraborty, Parimal Pal Chaudhuri, Samir Roy
    Delay Fault Test Generation with Cellular Automata. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:281-286 [Conf]
  16. Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan
    Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:11-13 [Conf]
  17. Supratik Chakraborty, Joycee Mekie, Dinesh K. Sharma
    Reasoning about synchronization in GALS systems. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2006, v:28, n:2, pp:153-169 [Journal]
  18. Supratik Chakraborty, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri
    Theory and Application of Nongroup Cellular Automata for Synthesis of Easily Testable Finite State Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:7, pp:769-781 [Journal]
  19. Supratik Chakraborty, Kenneth Y. Yun, David L. Dill
    Timing analysis of asynchronous systems using time separation of events. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:8, pp:1061-1076 [Journal]
  20. Kenneth Y. Yun, Kevin W. James, R. H. Fairlie-Cuninghame, Supratik Chakraborty, Rene L. Cruz
    A self-timed real-time sorting network. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:3, pp:356-363 [Journal]

  21. On Minimal Odd Rankings for Büchi Complementation. [Citation Graph (, )][DBLP]


  22. A Scalable Symbolic Simulator for Verilog RTL. [Citation Graph (, )][DBLP]


  23. Bottom-Up Shape Analysis. [Citation Graph (, )][DBLP]


  24. Bounding Variance and Expectation of Longest Path Lengths in DAGs. [Citation Graph (, )][DBLP]


  25. Automatically Refining Abstract Interpretations. [Citation Graph (, )][DBLP]


  26. On Semantic Generalizations of the Bernays-Schönfinkel-Ramsey Class with Finite or Co-finite Spectra [Citation Graph (, )][DBLP]


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