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Rajeev Murgai: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Supratik Chakraborty, Rajeev Murgai
    Layout-driven Timing Optimization by Generalized De Morgan Transform. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:647-654 [Conf]
  2. Rajeev Murgai
    Efficient global fanout optimization algorithms. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:571-576 [Conf]
  3. Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    An Improved Synthesis Algorithm for Multiplexor-Based PGA's. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:380-386 [Conf]
  4. Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Sequential Synthesis for Table Look Up Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:224-229 [Conf]
  5. Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Optimum Functional Decomposition Using Encoding. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:408-414 [Conf]
  6. Rajeev Murgai, Masahiro Fujita, Arlindo L. Oliveira
    Using Complementation and Resequencing to Minimize Transitions. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:694-697 [Conf]
  7. Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Logic Synthesis for Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:620-625 [Conf]
  8. Rajeev Murgai, Masahiro Fujita
    On Reducing Transitions Through Data Modifications. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:82-0 [Conf]
  9. Rajeev Murgai, Subodh M. Reddy, Takashi Miyoshi, Takeshi Horie, Mehdi Baradaran Tahoori
    Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:610-615 [Conf]
  10. Subodh M. Reddy, Gustavo R. Wilke, Rajeev Murgai
    Analyzing timing uncertainty in mesh-based clock architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1097-1102 [Conf]
  11. Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury
    Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:824-829 [Conf]
  12. Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita
    Speeding up technology-independent timing optimization by network partitioning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:83-90 [Conf]
  13. Hongyu Chen, Chao-Yang Yeh, Gustavo R. Wilke, Subodh M. Reddy, Hoa-van Nguyen, William W. Walker, Rajeev Murgai
    A sliding window scheme for accurate clock mesh analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:939-946 [Conf]
  14. Rajeev Murgai
    Layout-Driven Area-Constrained Timing Optimization by Net Buffering. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:379-386 [Conf]
  15. Rajeev Murgai
    Performance optimization under rise and fall parameters. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:185-190 [Conf]
  16. Rajeev Murgai
    On the global fanout optimization problem. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:511-515 [Conf]
  17. Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    On Clustering for Minimum Delay/Area. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:6-9 [Conf]
  18. Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Cube-packing and two-level minimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:115-122 [Conf]
  19. Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Improved Logic Synthesis Algorithms for Table Look Up Architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:564-567 [Conf]
  20. Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Performance Directed Synthesis for Table Look Up Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:572-575 [Conf]
  21. Arlindo L. Oliveira, Rajeev Murgai
    An Exact Gate Assignment Algorithm for Tree Circuits Under Rise and Fall Delays. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:451-457 [Conf]
  22. Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwini Verma
    XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:208-215 [Conf]
  23. Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Some Results on the Complexity of Boolean Functions for Table Look Up Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:505-512 [Conf]
  24. Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose
    Logic synthesis for a single large look-up table. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:415-0 [Conf]
  25. Rajeev Murgai, Fumiyasu Hirose, Masahiro Fujita
    Speeding Up Look-up-Table Driven Logic Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:385-397 [Conf]
  26. Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury
    Macromodeling of digital libraries for substrate noise analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:516-519 [Conf]
  27. Toshiyuki Shibuya, Rajeev Murgai, Tadashi Konno, Kazuhiro Emi, Kaoru Kawamura
    PDL: A New Physical Synthesis Methodology. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:348-0 [Conf]
  28. Chao-Yang Yeh, Gustavo R. Wilke, Hongyu Chen, Subodh M. Reddy, Hoa-van Nguyen, Takashi Miyoshi, William W. Walker, Rajeev Murgai
    Clock Distribution Architectures: A Comparative Study. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:85-91 [Conf]
  29. Gustavo R. Wilke, Rajeev Murgai
    Design and Analysis of "Tree+Local Meshes" Clock Architecture. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:165-170 [Conf]
  30. Rajeev Murgai
    Net Buffering in the Presence of Multiple Timing Views. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:367-372 [Conf]
  31. Supratik Chakraborty, Rajeev Murgai
    Complexity Of Minimum-Delay Gate Resizing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:425-430 [Conf]
  32. Supratik Chakraborty, Rajeev Murgai
    Layout-Driven Timing Optimization by Generalized De Morgan Transform. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:647-654 [Conf]
  33. Rajeev Murgai
    Delay-Constrained Area Recovery Via Layout-Driven Buffer Optimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:240-0 [Conf]
  34. Rajeev Murgai
    Net Buffering in the Presence of Multiple Timing Views. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:721-726 [Conf]
  35. Rajeev Murgai
    Improved Layout-Driven Area-Constrained Timing Optimization by Net Buffering. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:97-102 [Conf]
  36. Rajeev Murgai, Masahiro Fujita
    Some Recent Advances in Software and Hardware Logic Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:232-238 [Conf]
  37. Rajeev Murgai, Jawahar Jain, Masahiro Fujita
    Efficient Scheduling Techniques for ROBDD Construction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:394-401 [Conf]
  38. Subodh M. Reddy, Rajeev Murgai
    Accurate Substrate Noise Analysis Based on Library Module Characterization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:355-362 [Conf]
  39. Vineet Wason, Rajeev Murgai, William W. Walker
    An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:271-277 [Conf]
  40. Arlindo L. Oliveira, Rajeev Murgai
    On the problem of gate assignment under different rise and fall delays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:807-814 [Journal]
  41. Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury
    ADAMIN: automated, accurate macromodeling of digital aggressors for power and ground supply noise prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:56-64 [Journal]

  42. Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network. [Citation Graph (, )][DBLP]


  43. Fast power network analysis with multiple clock domains. [Citation Graph (, )][DBLP]


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