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Gi-Joon Nam: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chuck J. Alpert, Gi-Joon Nam, Paul Villarribua, Mehmet Can Yildiz
    Placement stability metrics. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1144-1147 [Conf]
  2. Seungbae Lee, Gi-Joon Nam, Junseok Chae, Hanseup Kim, Alan J. Drake
    Two-Dimensional Position Detection System with MEMS Accelerometer for MOUSE Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:852-857 [Conf]
  3. Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
    A boolean satisfiability-based incremental rerouting approach with application to FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:560-565 [Conf]
  4. Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
    Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:167-175 [Conf]
  5. Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
    Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:360-369 [Conf]
  6. Charles J. Alpert, Gi-Joon Nam, Paul Villarrubia
    Free space management for cut-based placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:746-751 [Conf]
  7. Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan
    An accurate sparse matrix based framework for statistical static timing analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:231-236 [Conf]
  8. Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia
    A semi-persistent clustering technique for VLSI circuit placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:200-207 [Conf]
  9. Gi-Joon Nam
    ISPD 2006 Placement Contest: Benchmark Suite and Results. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:167- [Conf]
  10. Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar
    A comparative study of two Boolean formulations of FPGA detailed routing constraints. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:222-227 [Conf]
  11. Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Bruce Winter, Mehmet Can Yildiz
    The ISPD2005 placement contest and benchmark suite. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:216-220 [Conf]
  12. Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
    Satisfiability-Based Detailed FPGA Routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:574-577 [Conf]
  13. Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar
    A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:6, pp:688-696 [Journal]
  14. Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia
    Effective free space management for cut-based placement via analytical constraint generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1343-1353 [Journal]
  15. Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng
    A Fast Hierarchical Quadratic Placement Algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:4, pp:678-691 [Journal]
  16. Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
    A new FPGA detailed routing approach via search-based Booleansatisfiability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:6, pp:674-684 [Journal]
  17. Seungbae Lee, Gi-Joon Nam, Junseok Chae, Hanseup Kim, Alan J. Drake
    Two-dimensional position detection system with MEMS accelerometers, readout circuitry, and microprocessor for padless mouse applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:10, pp:1167-1178 [Journal]
  18. Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris Chu
    RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:453-458 [Conf]
  19. Gi-Joon Nam, Mehmet Can Yildiz, David Z. Pan, Patrick H. Madden
    ISPD placement contest updates and ISPD 2007 global routing contest. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:167- [Conf]
  20. Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz
    The nuts and bolts of physical synthesis. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:89-94 [Conf]

  21. Hippocrates: First-Do-No-Harm Detailed Placement. [Citation Graph (, )][DBLP]


  22. Performance modeling for early analysis of multi-core systems. [Citation Graph (, )][DBLP]


  23. Detecting tangled logic structures in VLSI netlists. [Citation Graph (, )][DBLP]


  24. CRISP: Congestion reduction by iterated spreading during placement. [Citation Graph (, )][DBLP]


  25. Ispd2009 clock network synthesis contest. [Citation Graph (, )][DBLP]


  26. The ISPD global routing benchmark suite. [Citation Graph (, )][DBLP]


  27. RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. [Citation Graph (, )][DBLP]


  28. What makes a design difficult to route. [Citation Graph (, )][DBLP]


  29. ITOP: integrating timing optimization within placement. [Citation Graph (, )][DBLP]


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