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Srimat T. Chakradhar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Srimat T. Chakradhar
    Open architecture test system: not why but when! [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:337-340 [Conf]
  2. Seongmoon Wang, Srimat T. Chakradhar, Kedarnath J. Balakrishnan
    Re-configurable embedded core test protocol. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:234-237 [Conf]
  3. Arun Balakrishnan, Srimat T. Chakradhar
    Software transformations for sequential test generation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:266-0 [Conf]
  4. Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy
    Vector Restoration Using Accelerated Validation and Refinement. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:458-466 [Conf]
  5. Michael S. Hsiao, Srimat T. Chakradhar
    Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:452-457 [Conf]
  6. Joel Coburn, Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
    SECA: security-enhanced communication architecture. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:78-89 [Conf]
  7. Lei Yang, Robert P. Dick, Haris Lekatsas, Srimat T. Chakradhar
    CRAMES: compressed RAM for embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:93-98 [Conf]
  8. Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar
    Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:496-501 [Conf]
  9. Srimat T. Chakradhar, Sujit Dey
    Resynthesis and Retiming for Optimum Partial Scan. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:87-93 [Conf]
  10. Srimat T. Chakradhar, Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler
    Sequential Circuit Delay optimization Using Global Path Delays. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:483-489 [Conf]
  11. Srimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal
    Finite State Machine Synthesis with Fault Tolerant Test Function. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:562-567 [Conf]
  12. Srimat T. Chakradhar, Vishwani D. Agrawal
    A Transitive Closure Based Algorithm for Test Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:353-358 [Conf]
  13. Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell
    Automatic Test Generation Using Quadratic 0-1 Programming. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:654-659 [Conf]
  14. Srimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal
    An Exact Algorithm for Selecting Partial Scan Flip-Flops. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:81-86 [Conf]
  15. Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wen-Long Wei
    Unknown-tolerance analysis and test-quality control for test response compaction using space compactors. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1083-1088 [Conf]
  16. Haris Lekatsas, Jörg Henkel, Srimat T. Chakradhar, Venkata Jakkula, Murugan Sankaradass
    CoCo: a hardware/software platform for rapid prototyping of code compression technologies. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:306-311 [Conf]
  17. Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei, Kwang-Ting Cheng
    Coverage loss by using space compactors in presence of unknown values. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1053-1054 [Conf]
  18. Michael S. Hsiao, Srimat T. Chakradhar
    State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:577-582 [Conf]
  19. Seongmoon Wang, Kedarnath J. Balakrishnan, Srimat T. Chakradhar
    Efficient unknown blocking using LFSR reseeding. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1051-1052 [Conf]
  20. Seongmoon Wang, Xiao Liu, Srimat T. Chakradhar
    Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1296-1301 [Conf]
  21. Jiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar, Tiehan Lv
    A Case Study in Networks-on-Chip Design for Embedded Video. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:770-777 [Conf]
  22. Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan
    Signal Transition Graph Transformations for Initializability. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:670- [Conf]
  23. Vishwani D. Agrawal, Srimat T. Chakradhar
    Logic Simulation and Parallel Processing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:496-499 [Conf]
  24. Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy
    Static compaction using overlapped restoration and segment pruning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:140-146 [Conf]
  25. Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng
    Response shaper: a novel technique to enhance unknown tolerance for output response compaction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:80-87 [Conf]
  26. Anand Raghunathan, Srimat T. Chakradhar
    Acceleration techniques for dynamic vector compaction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:310-317 [Conf]
  27. Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan
    Initialization Isuues in the Synthesis of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:447-452 [Conf]
  28. Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng
    ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:147-152 [Conf]
  29. Jahangir Hasan, Srihari Cadambi, Venkata Jakkula, Srimat T. Chakradhar
    Chisel: A Storage-efficient, Collision-free Hash-based Network Processing Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:203-215 [Conf]
  30. Jiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar
    A methodology for design, modeling, and analysis of networks-on-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1778-1781 [Conf]
  31. Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy
    Static test sequence compaction based on segment reordering and accelerated vector restoration. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:954-0 [Conf]
  32. Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal
    A Synthesis Approach to Design for Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:754-763 [Conf]
  33. Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar
    Identification and Test Generation for Primitive Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:423-432 [Conf]
  34. Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar
    Design for Primitive Delay Fault Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:436-445 [Conf]
  35. Seongmoon Wang, Srimat T. Chakradhar
    A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:574-583 [Conf]
  36. Vishwani D. Agrawal, Srimat T. Chakradhar
    Performance estimation in a massively parallel system. [Citation Graph (0, 0)][DBLP]
    SC, 1990, pp:306-313 [Conf]
  37. Arun Balakrishnan, Srimat T. Chakradhar
    Partial scan design for technology mapped circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:283-287 [Conf]
  38. Arun Balakrishnan, Srimat T. Chakradhar
    Sequential Circuits with combinational Test Generation Complexity. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:111-117 [Conf]
  39. Arun Balakrishnan, Srimat T. Chakradhar
    Retiming with logic duplication transformation: theory and an application to partial scan. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:296-302 [Conf]
  40. Arun Balakrishnan, Srimat T. Chakradhar
    Peripheral Partitioning and Tree Decomposition for Partial Scan. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:181-186 [Conf]
  41. Kedarnath J. Balakrishnan, Seongmoon Wang, Srimat T. Chakradhar
    PIDISC: Pattern Independent Design Independent Seed Compression Technique. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:811-817 [Conf]
  42. Savita Banerjee, Srimat T. Chakradhar, Rabindra K. Roy
    Synchronous Test Generation Model for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:178-185 [Conf]
  43. Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan, Srimat T. Chakradhar
    Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:579-585 [Conf]
  44. Srimat T. Chakradhar, Vijay Gangaram, Steven G. Rothweiler
    Deriving Signal Constraints to Accelerate Sequential Test Generation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:488-494 [Conf]
  45. Srimat T. Chakradhar
    Optimum retiming of large sequential circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:135-140 [Conf]
  46. Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan
    Synthesis of Initializable Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:383-388 [Conf]
  47. Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy
    Resource-Constrained Compaction of Sequential Circuit Test Sets. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:398-405 [Conf]
  48. Jörg Henkel, Wayne Wolf, Srimat T. Chakradhar
    On-chip networks: A scalable, communication-centric embedded system design paradigm. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:845-0 [Conf]
  49. Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal
    A Test Function Architecture for Interconnected Finite State Machines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:113-116 [Conf]
  50. Haris Lekatsas, Jörg Henkel, Venkata Jakkula, Srimat T. Chakradhar
    A Unified Architecture for Adaptive Compression of Data and Code on Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:117-123 [Conf]
  51. Haris Lekatsas, Jörg Henkel, Venkata Jakkula, Srimat T. Chakradhar
    Using Shiftable Content Addressable Memories to Double Memory Capacity on Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:639-644 [Conf]
  52. Wei Li, Seongmoon Wang, Srimat T. Chakradhar, Sudhakar M. Reddy
    Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:471-478 [Conf]
  53. Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar
    Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:65-70 [Conf]
  54. Nachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar
    Accurate Power Macro-modeling Techniques for Complex RTL Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:235-241 [Conf]
  55. Anand Raghunathan, Srimat T. Chakradhar
    Dynamic test Sequence compaction for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:170-173 [Conf]
  56. Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
    Embedding Security in Wireless Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:269-270 [Conf]
  57. Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
    Efficient RTL Power Estimation for Large Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:431-439 [Conf]
  58. Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
    Tamper Resistance Mechanisms for Secure, Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:605-0 [Conf]
  59. Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell
    Zero Cost Test Point Insertion Technique for Structured ASICs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:357-363 [Conf]
  60. Srimat T. Chakradhar, Steven G. Rothweiler
    Redundancy Removal and Test Generation for Circuits with Non-Boolean Primitives. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:12-19 [Conf]
  61. Angela Krstic, Kwang-Ting (Tim) Cheng, Srimat T. Chakradhar
    Testing High Speed VLSI Devices Using Slower Testers. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:16-21 [Conf]
  62. Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell, Thomas K. Truong
    Neural Net and Boolean Satisfiability Models of Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1990, v:7, n:5, pp:54-57 [Journal]
  63. Haris Lekatsas, Jörg Henkel, Srimat T. Chakradhar, Venkata Jakkula
    Cypress: Compression and Encryption of Data and Code for Embedded Multimedia Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:5, pp:406-415 [Journal]
  64. Tiehan Lv, Jiang Xu, Wayne Wolf, Burak Ozer, Jörg Henkel, Srimat T. Chakradhar
    A Methodology for Architectural Design of Multimedia Multiprocessor SoCs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:1, pp:18-26 [Journal]
  65. Angela Krstic, Srimat T. Chakradhar, Kwang-Ting Cheng
    Testable Path Delay Fault Cover for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2000, v:16, n:5, pp:673-686 [Journal]
  66. Vishwani D. Agrawal, Srimat T. Chakradhar
    Combinational ATPG theorems for identifying untestable faults in sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1155-1160 [Journal]
  67. Srimat T. Chakradhar, Vishwani D. Agrawal, Steven G. Rothweiler
    A transitive closure algorithm for test generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:1015-1028 [Journal]
  68. Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal
    Toward massively parallel automatic test generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:9, pp:981-994 [Journal]
  69. Srimat T. Chakradhar, Sujit Dey
    Resynthesis and retiming for optimum partial scan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:621-630 [Journal]
  70. Srimat T. Chakradhar, Mahesh A. Iyer, Vishwani D. Agrawal
    Energy models for delay testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:728-739 [Journal]
  71. Srimat T. Chakradhar, Anand Raghunathan
    Bottleneck removal algorithm for dynamic compaction in sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1157-1172 [Journal]
  72. Srimat T. Chakradhar, Steven G. Rothweiler, Vishwani D. Agrawal
    Redundancy removal and test generation for circuits with non-Boolean primitives. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1370-1377 [Journal]
  73. Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal
    Test function embedding algorithms with application to interconnected finite state machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1115-1127 [Journal]
  74. Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal
    A partition and resynthesis approach to testable design of large circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:10, pp:1268-1276 [Journal]
  75. Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar
    Primitive delay faults: identification, testing, and design for testability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:669-684 [Journal]
  76. Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar
    Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2193-2206 [Journal]
  77. Seongmoon Wang, Srimat T. Chakradhar
    A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1555-1564 [Journal]
  78. Jiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. Chakradhar
    A design methodology for application-specific networks-on-chip. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:2, pp:263-280 [Journal]
  79. Vishwani D. Agrawal, Srimat T. Chakradhar
    Performance Analysis of Synchronized Iterative Algorithms on Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1992, v:3, n:6, pp:739-746 [Journal]
  80. Seongmoon Wang, Wenlong Wei, Srimat T. Chakradhar
    Unknown blocking scheme for low control data volume and high observability. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:33-38 [Conf]
  81. Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar
    Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:699-710 [Journal]
  82. Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan
    Synthesis of initializable asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:254-263 [Journal]

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