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Srinivas Katkoori: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Stelian Alupoaei, Srinivas Katkoori
    Net Clustering Based Macrocell Placement. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:399-406 [Conf]
  2. Suvodeep Gupta, Srinivas Katkoori
    A Fast Word-Level Statistical Estimator of Intra-Bus Crosstalk. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1110-1115 [Conf]
  3. Chandramouli Gopalakrishnan, Srinivas Katkoori
    Power Optimization of Combinational Circuits by Input Transformations. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:154-158 [Conf]
  4. Srinivas Katkoori, Ranga Vemuri
    Accurate Resource Estimation Algorithms for Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:338-339 [Conf]
  5. Chandramouli Gopalakrishnan, Srinivas Katkoori
    KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:430-435 [Conf]
  6. Srinivas Katkoori, Nand Kumar, Ranga Vemuri
    High level profiling based low power synthesis technique. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:446-0 [Conf]
  7. Ananth Durbha, Srinivas Katkoori
    RT-level Route-and-Place Design Methodology for Interconnect Optimization in DSM Regime. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:427-438 [Conf]
  8. Chandramouli Gopalakrishnan, Srinivas Katkoori
    Behavioral synthesis of datapaths with low leakage power. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:699-702 [Conf]
  9. Srinivas Katkoori, Ranga Vemuri
    Simulation based architectural power estimation for PLA-based controllers. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:121-124 [Conf]
  10. Vyas Krishnan, Srinivas Katkoori
    Design Space Exploration of RTL Datapaths Using Rent Parameter based Stochastic Wirelength Estimation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:364-369 [Conf]
  11. Vyas Krishnan, Srinivas Katkoori
    A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:885-892 [Conf]
  12. Chandramouli Gopalakrishnan, Srinivas Katkoori
    An Architectural Leakage Power Simulator for VHDL Structural Datapaths. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:211-212 [Conf]
  13. Ranganath Gopalan, Chandramouli Gopalakrishnan, Srinivas Katkoori
    Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:167-172 [Conf]
  14. Chandramouli Gopalakrishnan, Srinivas Katkoori
    Tabu Search Based Behavioral Synthesis of Low Leakage Datapaths. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:260-261 [Conf]
  15. Hao Li, Wai-Kei Mak, Srinivas Katkoori
    Force-Directed Performance-Driven Placement Algorithm for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:193-198 [Conf]
  16. Suvodeep Gupta, Srinivas Katkoori
    Force-Directed Scheduling for Dynamic Power Optimization. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:75-82 [Conf]
  17. Hariharan Sankaran, Srinivas Katkoori, Umadevi Kailasam
    System Level Energy Optimization for Location Aware Computing. [Citation Graph (0, 0)][DBLP]
    PerCom, 2005, pp:319-323 [Conf]
  18. Stelian Alupoaei, Srinivas Katkoori
    Net Clustering Based Macrocell Placement. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:399-0 [Conf]
  19. Stelian Alupoaei, Srinivas Katkoori
    Energy Model Based Macrocell Placement for Wirelength Minimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:713-716 [Conf]
  20. Stelian Alupoaei, Srinivas Katkoori
    Ant Colony Optimization Technique for Macrocell Overlap Removal. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:963-968 [Conf]
  21. Dinesh Bhatia, Ramesh Rajagopalan, Srinivas Katkoori
    Hierarchical Reconfiguration of VLSI/WSI Arrays. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:349-352 [Conf]
  22. Suvodeep Gupta, Srinivas Katkoori
    Intra-Bus Crosstalk Estimation Using Word-Level Statistics. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:449-454 [Conf]
  23. Suvodeep Gupta, Srinivas Katkoori, Hariharan Sankaran
    Floorplan-Based Crosstalk Estimation for Macrocell-Based Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:463-468 [Conf]
  24. Chandramouli Gopalakrishnan, Srinivas Katkoori
    Resource Allocation and Binding Approach for Low Leakage Power. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:297-302 [Conf]
  25. Srinivas Katkoori, Ranga Vemuri, Jay Roy
    A Hierarchical Register Optimization Algorithm for Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:126-132 [Conf]
  26. Soumyaroop Roy, Srinivas Katkoori, Nagarajan Ranganathan
    A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:215-220 [Conf]
  27. Didier Keymeulen, Ricardo Salem Zebulum, Rajeshuni Ramesham, Adrian Stoica, Srinivas Katkoori, Sharon Graves, Frank Novak, Charles Antill
    Self-Adaptive System Based on Field Programmable Gate Array for Extreme Temperature Electronics. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:296-300 [Conf]
  28. Adrian Stoica, Ricardo Salem Zebulum, Didier Keymeulen, Rajeshuni Ramesham, Joseph Neff, Srinivas Katkoori
    Temperature-Adaptive Circuits on Reconfigurable Analog Arrays. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:28-31 [Conf]
  29. Nand Kumar, Srinivas Katkoori, Leo Rader, Ranga Vemuri
    Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:3, pp:70-84 [Journal]
  30. Suvodeep Gupta, Srinivas Katkoori
    Intrabus crosstalk estimation using word-level statistics. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:469-478 [Journal]
  31. Vyas Krishnan, Srinivas Katkoori
    A genetic algorithm for the design space exploration of datapaths during high-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Evolutionary Computation, 2006, v:10, n:3, pp:213-229 [Journal]
  32. Hao Li, Srinivas Katkoori, Wai-Kei Mak
    Power minimization algorithms for LUT-based FPGA technology mapping. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2004, v:9, n:1, pp:33-51 [Journal]
  33. Ranga Vemuri, Srinivas Katkoori, Meenakshi Kaul, Jay Roy
    An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:1, pp:189-216 [Journal]
  34. Stelian Alupoaei, Srinivas Katkoori
    Ant colony system application to macrocell overlap removal. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1118-1123 [Journal]
  35. Adrian Stoica, Didier Keymeulen, Ricardo Salem Zebulum, Mohammad Mojarradi, Srinivas Katkoori, Taher Daud
    Adaptive and Evolvable Analog Electronics for Space Applications. [Citation Graph (0, 0)][DBLP]
    ICES, 2007, pp:379-390 [Conf]
  36. Stelian Alupoaei, Srinivas Katkoori
    Net-based force-directed macrocell placement for wirelength optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:824-835 [Journal]

  37. Bus Binding, Re-ordering, and Encoding for Crosstalk-Producing Switching Activity Minimization during High Level Synthesis. [Citation Graph (, )][DBLP]

  38. Self-Reconfigurable Mixed-Signal Integrated Circuits Architecture Comprising a Field Programmable Analog Array and a General Purpose Genetic Algorithm IP Core. [Citation Graph (, )][DBLP]

  39. A customizable FPGA IP core implementation of a general purpose Genetic Algorithm engine. [Citation Graph (, )][DBLP]

  40. On-chip dynamic worst-case crosstalk pattern detection and elimination for bus-based macro-cell designs. [Citation Graph (, )][DBLP]

  41. Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis. [Citation Graph (, )][DBLP]

  42. Minimizing wire delays by net-topology aware binding during floorplan- driven high level synthesis. [Citation Graph (, )][DBLP]

  43. Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis. [Citation Graph (, )][DBLP]

  44. An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning. [Citation Graph (, )][DBLP]

  45. Simultaneous Peak Temperature and Average Power Minimization during Behavioral Synthesis. [Citation Graph (, )][DBLP]

  46. "Glitch Logic" and Applications to Computing and Information Security. [Citation Graph (, )][DBLP]

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