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C. P. Ravikumar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. S. Chakraverty, C. P. Ravikumar, D. Roy Choudhuri
    An Evolutionary Scheme for Cosynthesis of Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:251-260 [Conf]
  2. Rahul Kumar, C. P. Ravikumar
    Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:45-50 [Conf]
  3. C. P. Ravikumar, Rahul Kumar
    Divide-and-Conquer IDDQ Testing for Core-based System Chips. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:761-766 [Conf]
  4. Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri
    Improvement of ASIC Design Processes. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:105-112 [Conf]
  5. Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar
    Partial Gating Optimization for Power Reduction During Test Application. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:242-247 [Conf]
  6. Rajesh Kannah, C. P. Ravikumar
    Functional Testing of Microprocessors with Graded Fault Coverage. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:204-0 [Conf]
  7. C. P. Ravikumar, N. Satya Prasad
    Evaluating BIST Architectures for Low Power. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:430-434 [Conf]
  8. C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal
    A STAFAN-like functional testability measure for register-level circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:192-198 [Conf]
  9. C. P. Ravikumar, Ashutosh Verma, Gaurav Chandra
    A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:107-112 [Conf]
  10. Nidhi Agrawal, C. P. Ravikumar
    Adaptive Routing Based on Deadlock Recovery. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1998, pp:981-988 [Conf]
  11. Nidhi Agrawal, Parul Agarwal, C. P. Ravikumar
    Efficient Delay Test Generation for Modular Circuits. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:220-0 [Conf]
  12. Rohit Sharma, C. P. Ravikumar
    Design Issues in Synthesis of Reusable Cores. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:144-0 [Conf]
  13. Nishit Narang, Girish Kumar, C. P. Ravikumar
    Efficient Algorithms for Delay Bounded Multicast Tree Generation for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    HiPC, 1999, pp:169-173 [Conf]
  14. C. P. Ravikumar, Meeta Sharma, Prachi Jain
    Design of WDM Networks for Delay-Bound Multicasting. [Citation Graph (0, 0)][DBLP]
    HiPC, 1999, pp:399-403 [Conf]
  15. Aman Kokrady, C. P. Ravikumar
    Static Verification of Test Vectors for IR Drop Failure. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:760-764 [Conf]
  16. Nidhi Agrawal, C. P. Ravikumar
    An Euler Path Based Technique for Deadlock-free Multicasting. [Citation Graph (0, 0)][DBLP]
    ICPP, 1997, pp:378-384 [Conf]
  17. C. P. Ravikumar, A. Kuchlous, G. Manimaran
    Incomplete Star Graph: An Economical Fault-tolerant Interconnection Network. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:83-90 [Conf]
  18. C. P. Ravikumar, Lalit M. Patnaik
    An Architecture for CSP and Its Simulation. [Citation Graph (0, 0)][DBLP]
    ICPP, 1987, pp:874-881 [Conf]
  19. C. P. Ravikumar, Sarma Sastry
    Parallel Placement on Hypercube Architecture. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1989, pp:97-101 [Conf]
  20. C. P. Ravikumar
    A Parallel Search-and-Learn Technique for Solving Large Scale TSP. [Citation Graph (0, 0)][DBLP]
    ICTAI, 1993, pp:381-388 [Conf]
  21. C. P. Ravikumar, Graham Hetherington
    A Holistic Parallel and Hierarchical Approach towards Design-For-Test. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:345-354 [Conf]
  22. Mirza Mohd. Sufyan Beg, C. P. Ravikumar
    Measuring the Quality of Web Search Results. [Citation Graph (0, 0)][DBLP]
    JCIS, 2002, pp:324-328 [Conf]
  23. S. Chakraverty, C. P. Ravikumar
    A Stochastic Framework for Co-synthesis of Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    LCTES, 2000, pp:96-113 [Conf]
  24. Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
    A Novel BIST Architecture With Built-in Self Check. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:57-60 [Conf]
  25. Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
    Efficient Implementation of Multiple On-Chip Signature Checking. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:297-302 [Conf]
  26. Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
    Hybrid Testing Schemes Based on Mutual and Signature Testing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:293-0 [Conf]
  27. Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
    On-Chip Signature Checking for Embedded Memories. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:558-563 [Conf]
  28. S. Chakraverty, C. P. Ravikumar, D. Roy Choudhuri
    An Evolutionary Scheme for Cosynthesis of Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:251-0 [Conf]
  29. Vishal Dalal, C. P. Ravikumar
    Software Power Optimizations In An Embedded System. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:254-0 [Conf]
  30. Dong-Hyun Heo, Alice C. Parker, C. P. Ravikumar
    Rapid Synthesis of Multi-Chip Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:62-68 [Conf]
  31. Dong-Hyun Heo, Alice C. Parker, C. P. Ravikumar
    An Evolutionary Approach to System Redesign. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:359-0 [Conf]
  32. Aman Kokrady, C. P. Ravikumar
    Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:597-0 [Conf]
  33. Rahul Kumar, C. P. Ravikumar
    Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:45-50 [Conf]
  34. C. P. Ravikumar
    Multiprocessor Architectures for Embedded System-on-chip Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:512-519 [Conf]
  35. C. P. Ravikumar, R. Aggarwal, C. Sharma
    A Graph-Theoretic Approach for Register File Based Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:118-123 [Conf]
  36. C. P. Ravikumar, Gaurav Chandra, Ashutosh Verma
    Simultaneous Module Selection and Scheduling for Power-Constrained Testing of Core Based Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:462-467 [Conf]
  37. C. P. Ravikumar, R. Dandamudi, V. R. Devanathan, N. Haldar, K. Kiran, P. S. Vijay Kumar
    A Framework for Distributed and Hierarchical Design-for-Test. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:497-503 [Conf]
  38. C. P. Ravikumar, Sumit Gupta, Akshay Jajoo
    Synthesis of Testable RTL Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:187-192 [Conf]
  39. C. P. Ravikumar, Hemant Joshi
    HISCOAP: a hierarchical testability analysis tool. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:272-277 [Conf]
  40. C. P. Ravikumar, Vikas Jain, Anurag Dod
    Faster Fault Simulation Through Distributed Computing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:482-487 [Conf]
  41. C. P. Ravikumar, Rahul Kumar
    Divide-and-Conquer IDDQ Testing for Core-Based System Chips. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:761-766 [Conf]
  42. C. P. Ravikumar, Nitin Kakkar, Saurabh Chopra
    Mutual Testing based on Wavelet Transforms. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:347-352 [Conf]
  43. C. P. Ravikumar, Ajay Mittal
    Hierarchical Delay Fault Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:635-0 [Conf]
  44. C. P. Ravikumar, Mukul R. Prasad, Lavmeet S. Hora
    Estimation of Power from Module-level Netlists. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:324-325 [Conf]
  45. C. P. Ravikumar, H. Rasheed
    Simulated Annealing for Target-Oriented Scan. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:107-112 [Conf]
  46. C. P. Ravikumar, Rajamani Rajarajan
    Genetic Algorithms for Scan Path Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:118-121 [Conf]
  47. C. P. Ravikumar, V. Saxena
    Synthesis of Testable Pipelined Datapaths Using Genetic Search. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:205-210 [Conf]
  48. C. P. Ravikumar, Manish Sharma, R. K. Patney
    Improving the Diagnosability of Digital Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:629-634 [Conf]
  49. Vineet Sahula, C. P. Ravikumar
    The Hierarchical Concurrent Flow Graph Approach for Modeling and Analysis of Design Processes. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:91-96 [Conf]
  50. Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri
    Improvement of ASIC Design Processes. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:105-0 [Conf]
  51. Anil Sharma, C. P. Ravikumar
    Efficient Implementation of ADPCM Codec. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:456-461 [Conf]
  52. V. Sankara Subramanian, C. P. Ravikumar
    Estimating Crosstalk From Vlsi Layouts. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:531-0 [Conf]
  53. Suhrid A. Wadekar, Alice C. Parker, C. P. Ravikumar
    Freedom: Statistical Behavioral Estimation of System Energy and Power. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:30-36 [Conf]
  54. V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
    Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:351-356 [Conf]
  55. T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan
    MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:527-533 [Conf]
  56. Nisar Ahmed, C. P. Ravikumar, Mohammad Tehranipoor, Jim Plusquellic
    At-Speed Transition Fault Testing With Low Speed Scan Enable. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:42-47 [Conf]
  57. V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
    Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:167-172 [Conf]
  58. C. P. Ravikumar
    Interval partition with bounded overlap. [Citation Graph (0, 0)][DBLP]
    Computer-Aided Design, 1992, v:24, n:8, pp:405-410 [Journal]
  59. C. P. Ravikumar
    Solving VLSI physical design problems on a vector machine. [Citation Graph (0, 0)][DBLP]
    Computer-Aided Design, 1993, v:25, n:1, pp:49-57 [Journal]
  60. C. P. Ravikumar, Rajneesh Bajpai
    Source-based delay-bounded multicasting in multimedia networks. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 1998, v:21, n:2, pp:126-132 [Journal]
  61. C. P. Ravikumar, Tarun Rai, Varun Verma
    Kautz graphs as attractive logical topologies in multihop lightwave networks. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 1997, v:20, n:14, pp:1259-1270 [Journal]
  62. C. P. Ravikumar, Lalit M. Patnaik
    Performance improvement of simulated annealing algorithms. [Citation Graph (0, 0)][DBLP]
    Comput. Syst. Sci. Eng., 1990, v:5, n:2, pp:111-115 [Journal]
  63. Mitra Subhasish, Ondrej Novák, Hana Kubatova, Bashir M. Al-Hashimi, Erik Jan Marinissen, C. P. Ravikumar
    Conference Reports. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:4, pp:262-265 [Journal]
  64. Mohammed Fadle Abdulla, C. P. Ravikumar
    A self-checking signature scheme for checking backdoor security attacks in Internet. [Citation Graph (0, 0)][DBLP]
    J. High Speed Networks, 2004, v:13, n:4, pp:309-317 [Journal]
  65. C. P. Ravikumar
    Parallel search-and-learn technique for solving large scale travelling-salesperson problems. [Citation Graph (0, 0)][DBLP]
    Knowl.-Based Syst., 1994, v:7, n:3, pp:169-176 [Journal]
  66. C. P. Ravikumar, R. Aggarwal
    Parallel search-and-learn techniques and graph coloring. [Citation Graph (0, 0)][DBLP]
    Knowl.-Based Syst., 1996, v:9, n:1, pp:3-13 [Journal]
  67. V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
    Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:534-539 [Conf]
  68. Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar
    A critical-path-aware partial gating approach for test power reduction. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:2, pp:- [Journal]
  69. V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
    On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:464-476 [Journal]
  70. Arasu T. Senthil, C. P. Ravikumar, S. K. Nandy
    Low-Power Hierarchical Scan Test for Multiple Clock Domains. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:106-118 [Journal]

  71. MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip. [Citation Graph (, )][DBLP]


  72. Test Strategies for Low Power Devices. [Citation Graph (, )][DBLP]


  73. A scheme for multiple on-chip signature checking for embedded SRAMs. [Citation Graph (, )][DBLP]


  74. Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models. [Citation Graph (, )][DBLP]


  75. Memory Architecture Exploration Framework for Cache Based Embedded SOC. [Citation Graph (, )][DBLP]


  76. Conference Reports. [Citation Graph (, )][DBLP]


  77. Variation-Tolerant, Power-Safe Pattern Generation. [Citation Graph (, )][DBLP]


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