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Farid N. Najm: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jason Helge Anderson, Farid N. Najm
    Interconnect capacitance estimation for FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:713-718 [Conf]
  2. David Blaauw, Anirudh Devgan, Farid N. Najm
    Leakage power: trends, analysis and avoidance. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:- [Conf]
  3. Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm
    Variations-aware low-power design with voltage scaling. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:529-534 [Conf]
  4. Navid Azizi, Farid N. Najm
    A family of cells to reduce the soft-error-rate in ternary-CAM. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:779-784 [Conf]
  5. Srinivas Bodapati, Farid N. Najm
    High-level current macro-model for power-grid analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:385-390 [Conf]
  6. Richard Burch, Farid N. Najm, Ping Yang, Dale E. Hocevar
    Pattern-Independent Current Estimation for Reliability Analysis of CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:294-299 [Conf]
  7. Imad A. Ferzli, Farid N. Najm
    Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:856-859 [Conf]
  8. Subodh Gupta, Farid N. Najm
    Power Macromodeling for High Level Power Estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:365-370 [Conf]
  9. Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm
    Worst-case circuit delay taking into account power supply variations. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:652-657 [Conf]
  10. Dionysios Kouroussis, Farid N. Najm
    A static pattern-independent technique for power grid voltage integrity verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:99-104 [Conf]
  11. Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj
    Maximum Current Estimation in CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:2-7 [Conf]
  12. Harish Kriplani, Farid N. Najm, Ping Yang, Ibrahim N. Hajj
    Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:384-388 [Conf]
  13. Georges Nabaa, Navid Azizi, Farid N. Najm
    An adaptive FPGA architecture with process variation compensation and reduced leakage. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:624-629 [Conf]
  14. Farid N. Najm
    On the need for statistical timing analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:764-765 [Conf]
  15. Farid N. Najm
    Transition Density, A Stochastic Measure of Activity in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:644-649 [Conf]
  16. Farid N. Najm
    Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:612-617 [Conf]
  17. Farid N. Najm, Shashank Goel, Ibrahim N. Hajj
    Power Estimation in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:635-640 [Conf]
  18. Farid N. Najm, Noel Menezes
    Statistical timing analysis based on a timing yield model. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:460-465 [Conf]
  19. Farid N. Najm, Michael Y. Zhang
    Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:623-627 [Conf]
  20. Mahadevamurty Nemani, Farid N. Najm
    Delay Estimation VLSI Circuits from a High-Level View. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:591-594 [Conf]
  21. Rajendran Panda, Farid N. Najm
    Technology-Dependent Transformations for Low-Power Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:650-655 [Conf]
  22. Bin Wu, Jianwen Zhu, Farid N. Najm
    An analytical approach for dynamic range estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:472-477 [Conf]
  23. Bin Wu, Jianwen Zhu, Farid N. Najm
    A non-parametric approach for dynamic range estimation of nonlinear systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:841-844 [Conf]
  24. Michael G. Xakellis, Farid N. Najm
    Statistical Estimation of the Switching Activity in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:728-733 [Conf]
  25. Jason Helge Anderson, Farid N. Najm, Tim Tuan
    Active leakage power optimization for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:33-41 [Conf]
  26. Rubil Ahmadi, Farid N. Najm
    Timing Analysis in Presence of Power Supply and Ground Voltage Variations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:176-183 [Conf]
  27. Jason Helge Anderson, Farid N. Najm
    Low-power programmable routing circuitry for FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:602-609 [Conf]
  28. Richard Burch, Farid N. Najm, Ping Yang, Timothy N. Trick
    McPOWER: a Monte Carlo approach to power estimation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:90-97 [Conf]
  29. Imad A. Ferzli, Farid N. Najm
    Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:770-777 [Conf]
  30. Khaled R. Heloue, Farid N. Najm
    Statistical timing analysis with two-sided constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:829-836 [Conf]
  31. Dionysios Kouroussis, Imad A. Ferzli, Farid N. Najm
    Incremental partitioning-based vectorless power grid verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:358-364 [Conf]
  32. Joseph N. Kozhaya, Farid N. Najm
    Accurate power estimation for large sequential circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:488-493 [Conf]
  33. Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm
    Multigrid-Like Technique for Power Grid Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:480-487 [Conf]
  34. Farid N. Najm
    Power estimation techniques for integrated circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:492-499 [Conf]
  35. Mahadevamurty Nemani, Farid N. Najm
    High-level area and power estimation for VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:114-119 [Conf]
  36. Bin Wu, Jianwen Zhu, Farid N. Najm
    Dynamic range estimation for nonlinear systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:660-667 [Conf]
  37. Sari Onaissi, Farid N. Najm
    A linear-time approach for static timing analysis covering all process corners. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:217-224 [Conf]
  38. Nahi H. Abdul Ghani, Farid N. Najm
    Handling inductance in early power grid verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:127-134 [Conf]
  39. Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj
    Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:435-438 [Conf]
  40. Kavel M. Büyüksahin, Farid N. Najm
    High-level power estimation with interconnect effects. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:197-202 [Conf]
  41. Kavel M. Büyüksahin, Farid N. Najm
    High-level area estimation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:271-274 [Conf]
  42. Kavel M. Büyüksahin, Priyadarsan Patra, Farid N. Najm
    ESTIMA: an architectural-level power estimator for multi-ported pipelined register files. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:294-297 [Conf]
  43. Navid Azizi, Andreas Moshovos, Farid N. Najm
    Low-leakage asymmetric-cell SRAM. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:48-51 [Conf]
  44. Srinivas Bodapati, Farid N. Najm
    Frequency-domain supply current macro-model. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:295-298 [Conf]
  45. Subodh Gupta, Farid N. Najm
    Power macro-models for DSP blocks with application to high-level synthesis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:103-105 [Conf]
  46. Subodh Gupta, Farid N. Najm
    Energy-per-cycle estimation at RTL. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:121-126 [Conf]
  47. Farid N. Najm
    Towards a high-level power estimation capability. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:87-92 [Conf]
  48. Mahadevamurty Nemani, Farid N. Najm
    High-level power estimation and the area complexity of Boolean functions. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:329-334 [Conf]
  49. Maha Nizam, Farid N. Najm, Anirudh Devgan
    Power grid voltage integrity verification. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:239-244 [Conf]
  50. Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm
    An optimization technique for dual-output domino logic. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:258-260 [Conf]
  51. Navid Azizi, Farid N. Najm
    An Asymmetric SRAM Cell to Lower Gate Leakage. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:534-539 [Conf]
  52. Rafik S. Guindi, Farid N. Najm
    Design Techniques for Gate-Leakage Reduction in CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:61-0 [Conf]
  53. Gilbert Yoh, Farid N. Najm
    A Statistical Model for Electromigration Failures. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:45-50 [Conf]
  54. Jason Helge Anderson, Farid N. Najm
    Switching activity analysis and pre-layout activity prediction for FPGAs. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:15-21 [Conf]
  55. Srinivas Bodapati, Farid N. Najm
    Pre-layout estimation of individual wire lengths. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:93-98 [Conf]
  56. Jason Helge Anderson, Farid N. Najm
    Active leakage power optimization for FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:423-437 [Journal]
  57. Srinivas Bodapati, Farid N. Najm
    High-level current macro model for logic blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:837-855 [Journal]
  58. Kavel M. Büyüksahin, Farid N. Najm
    Early power estimation for VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:7, pp:1076-1088 [Journal]
  59. Imad A. Ferzli, Farid N. Najm
    Analysis and verification of power grids considering process-induced leakage-current variations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:126-143 [Journal]
  60. Subodh Gupta, Farid N. Najm
    Analytical models for RTL power estimation of combinational andsequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:808-814 [Journal]
  61. Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm
    Voltage-Aware Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2156-2169 [Journal]
  62. Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm
    A multigrid-like technique for power grid analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1148-1160 [Journal]
  63. Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj
    Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:8, pp:998-1012 [Journal]
  64. Mahadevamurty Nemani, Farid N. Najm
    Towards a high-level power estimation capability [digital ICs]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:6, pp:588-598 [Journal]
  65. Mahadevamurty Nemani, Farid N. Najm
    High-level area and power estimation for VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:697-713 [Journal]
  66. Farid N. Najm
    Transition density: a new measure of activity in digital circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:310-323 [Journal]
  67. Farid N. Najm
    Low-pass filter for computing the transition density in digital circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1123-1131 [Journal]
  68. Farid N. Najm, Richard Burch, Ping Yang, Ibrahim N. Hajj
    Probabilistic simulation for reliability analysis of CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:439-450 [Journal]
  69. Farid N. Najm, Ibrahim N. Hajj
    The complexity of fault detection in MOS VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:9, pp:995-1001 [Journal]
  70. Farid N. Najm, Ibrahim N. Hajj, Ping Yang
    An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:11, pp:1372-1381 [Journal]
  71. Bin Wu, Jianwen Zhu, Farid N. Najm
    Dynamic-range estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1618-1636 [Journal]
  72. Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj
    Estimation of state line statistics in sequential circuits. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:3, pp:455-473 [Journal]
  73. Jason Helge Anderson, Farid N. Najm
    Power estimation techniques for FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1015-1027 [Journal]
  74. Andreas Moshovos, Babak Falsafi, Farid N. Najm, Navid Azizi
    A Case for Asymmetric-Cell Cache Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:7, pp:877-881 [Journal]
  75. Khaled R. Heloue, Navid Azizi, Farid N. Najm
    Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:93-98 [Conf]
  76. Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir
    Maximum circuit activity estimation using pseudo-boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1538-1543 [Conf]
  77. Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm
    Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:7, pp:746-757 [Journal]
  78. Richard Burch, Farid N. Najm, Ping Yang, Timothy N. Trick
    A Monte Carlo approach for power estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:1, pp:63-71 [Journal]
  79. Farid N. Najm
    A survey of power estimation techniques in VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:446-455 [Journal]
  80. Subodh Gupta, Farid N. Najm
    Power modeling for high-level power estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:18-29 [Journal]
  81. Joseph N. Kozhaya, Farid N. Najm
    Power estimation for large sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:400-407 [Journal]
  82. Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm
    A technique for Improving dual-output domino logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:508-511 [Journal]
  83. Navid Azizi, Farid N. Najm, Andreas Moshovos
    Low-leakage asymmetric-cell SRAM. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:701-715 [Journal]
  84. Subodh Gupta, Farid N. Najm
    Energy and peak-current per-cycle estimation at RTL. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:525-537 [Journal]

  85. Parameterized timing analysis with general delay models and arbitrary variation sources. [Citation Graph (, )][DBLP]


  86. Clock skew optimization via wiresizing for timing sign-off covering all process corners. [Citation Graph (, )][DBLP]


  87. Fast vectorless power grid verification using an approximate inverse technique. [Citation Graph (, )][DBLP]


  88. Monte-Carlo approach for power estimation in sequential circuits. [Citation Graph (, )][DBLP]


  89. A geometric approach for early power grid verification using current constraints. [Citation Graph (, )][DBLP]


  90. Efficient block-based parameterized timing analysis covering all potentially critical paths. [Citation Graph (, )][DBLP]


  91. PSTA-based branch and bound approach to the silicon speedpath isolation problem. [Citation Graph (, )][DBLP]


  92. Quantifying robustness metrics in parameterized static timing analysis. [Citation Graph (, )][DBLP]


  93. Early power grid verification under circuit current uncertainties. [Citation Graph (, )][DBLP]


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