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Yen-Jen Chang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yen-Jen Chang
    Lazy BTB: reduce BTB energy consumption using dynamic profiling. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:917-922 [Conf]
  2. Yen-Jen Chang
    An ultra low-power TLB design. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1122-1127 [Conf]
  3. Yen-Jen Chang, Chia-Lin Yang, Feipei Lai
    Value-Conscious Cache: Simple Technique for Reducing Cache Access Power. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:16-21 [Conf]
  4. Yen-Jen Chang, Feipei Lai, Shanq-Jang Ruan
    Cache Design for Eliminating the Address Translation Bottleneck and Reducing the Tag Area Cost. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:334-339 [Conf]
  5. Yen-Jen Chang, Chia-Lin Yang, Feipei Lai
    A power-aware SWDR cell for reducing cache write power. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:14-17 [Conf]
  6. Yen-Jen Chang, Feipei Lai, Shanq-Jang Ruan
    An Efficient Two-Level Filter Scheme for Low Power Cache. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:61-66 [Conf]
  7. Yen-Jen Chang, Yung-Ching Weng, Feipei Lai
    Enhanced object management for high performance web proxies. [Citation Graph (0, 0)][DBLP]
    SAC, 2004, pp:1711-1716 [Conf]
  8. Yen-Jen Chang
    An Alternative Real-Time Filter Scheme to Block Buffering. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:762-765 [Conf]
  9. Yen-Jen Chang, Feipei Lai
    Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:4, pp:20-32 [Journal]
  10. Yen-Jen Chang, Feipei Lai, Chia-Lin Yang
    Zero-aware asymmetric SRAM cell for reducing cache power in writing zero. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:8, pp:827-836 [Journal]
  11. Yen-Jen Chang, Yuan-Hong Liao, Shanq-Jang Ruan
    Improve CAM power efficiency using decoupled match line scheme. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:165-170 [Conf]
  12. Yen-Jen Chang, Maofeng Lan
    Two New Techniques Integrated for Energy-Efficient TLB Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:13-23 [Journal]
  13. Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Feipei Lai, Uwe Schwiegelshohn
    ENPCO: an entropy-based partition-codec algorithm to reduce power for bipartition-codec architecture in pipelined circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:942-949 [Journal]
  14. Yen-Jen Chang, Shanq-Jang Ruan, Feipei Lai
    Design and analysis of low-power cache using two-level filter scheme. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:568-580 [Journal]

  15. A Novel High Performance Ternary CAM (TCAM) for LPM. [Citation Graph (, )][DBLP]

  16. Low Power Selected Gating Frame Buffer (SGFB) Design. [Citation Graph (, )][DBLP]

  17. Exploiting frequent opcode locality for power efficient instruction cache. [Citation Graph (, )][DBLP]

  18. Paged cache: an efficient partition architecture for reducing power, area and access time. [Citation Graph (, )][DBLP]

  19. Energy analysis of bipartition architecture for pipelined circuits. [Citation Graph (, )][DBLP]

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