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TingTing Hwang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tsuang-Wei Chang, TingTing Hwang, Sheng-Yu Hsu
    Functionality directed clustering for low power MTCMOS design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:862-867 [Conf]
  2. Yen-Te Ho, TingTing Hwang
    Low power design using dual threshold voltage. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:205-208 [Conf]
  3. Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang
    Switching-activity driven gate sizing and Vth assignment for low power design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:576-581 [Conf]
  4. Shiuann-Shiuh Lin, Wen-Hsin Chen, Wen-Wei Lin, TingTing Hwang
    A Clustering Based Linear Ordering Algorithm for K-Way Spectral Partitioning. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:77-80 [Conf]
  5. How-Rern Lin, TingTing Hwang
    Power recduction by gate sizing with path-oriented slack calculation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  6. LiYi Lin, Yi-Yu Liu, TingTing Hwang
    A construction of minimal delay Steiner tree using two-pole delay model. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:126-132 [Conf]
  7. Yi-Ping You, Chun-Yen Tseng, Yu-Hui Huang, Po-Chiun Huang, TingTing Hwang, Sheng-Yu Hsu
    Low-power techniques for network security processors. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:355-360 [Conf]
  8. Wen-Wen Hsieh, Po-Yuan Chen, TingTing Hwang
    A bus architecture for crosstalk elimination in high performance processor design. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2006, pp:247-252 [Conf]
  9. Chau-Shen Chen, TingTing Hwang, C. L. Liu
    Low Power FPGA Design - A Re-engineering Approach. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:656-661 [Conf]
  10. Chau-Shen Chen, Kuang-Hui Lin, TingTing Hwang
    Layout Driven Selecting and Chaining of Partial Scan. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:262-267 [Conf]
  11. Jan-Min Hwang, Feng-Yi Chiang, TingTing Hwang
    A Re-engineering Approach to Low Power FPGA Design Using SPFD. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:722-725 [Conf]
  12. TingTing Hwang, Robert Michael Owens, Mary Jane Irwin
    Multi-Level Logic Synthesis Using Communication Complexity. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:215-220 [Conf]
  13. Kuo-Hua Wang, TingTing Hwang
    Boolean Matching for Incompletely Specified Functions. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:48-53 [Conf]
  14. Alex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang
    G-MAC: An Application-Specific MAC/Co-Processor Synthesizer. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11134-11135 [Conf]
  15. Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu
    Logic Transformation for Low Power Synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:158-162 [Conf]
  16. Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
    Decomposition of Instruction Decoder for Low Power Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:664-665 [Conf]
  17. MingHung Lee, TingTing Hwang, Shi-Yu Huang
    Decomposition of Extended Finite State Machine for Low Power Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11152-11153 [Conf]
  18. Yi-Yu Liu, TingTing Hwang
    Crosstalk-aware domino logic synthesis. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1312-1317 [Conf]
  19. Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang
    Crosstalk Minimization in Logic Synthesis for PLA. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:790-795 [Conf]
  20. Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu
    Binary decision diagram with minimum expected path length. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:708-712 [Conf]
  21. Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang
    A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11102-11103 [Conf]
  22. How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang
    Cell Height Driven Transistor Sizing in a Cell Based Module Design. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:425-429 [Conf]
  23. Chau-Shen Chen, TingTing Hwang, C. L. Liu
    Architecture driven circuit partitioning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:408-411 [Conf]
  24. Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
    Combining technology mapping and placement for delay-optimization in FPGA designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:123-127 [Conf]
  25. How-Rern Lin, TingTing Hwang
    Dynamical identification of critical paths for iterative gate sizing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:481-484 [Conf]
  26. Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
    State Assignment for Power and Area Minimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:250-254 [Conf]
  27. Chi-Wei Hu, TingTing Hwang
    Output-pattern directed decomposition for low power design. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:137-140 [Conf]
  28. Chi Ta Wu, TingTing Hwang
    Instruction buffering for nested loops in low power design. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:81-84 [Conf]
  29. Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai
    Compiler Optimization on Instruction Scheduling for Low Power. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:55-61 [Conf]
  30. Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei-Kuan Shih, TingTing Hwang
    Power-Aware Scheduling for Parallel Security Processors with Analytical Models. [Citation Graph (0, 0)][DBLP]
    LCPC, 2004, pp:470-484 [Conf]
  31. Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin, TingTing Hwang
    ELM-A Fast Addition Algorithm Discovered by a Program. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:9, pp:1181-1184 [Journal]
  32. Shih-Chieh Chang, Malgorzata Marek-Sadowska, TingTing Hwang
    Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1226-1236 [Journal]
  33. Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
    Combining technology mapping and placement for delay-minimization in FPGA designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1076-1084 [Journal]
  34. TingTing Hwang, Robert Michael Owens, Mary Jane Irwin
    Exploiting communication complexity for multilevel logic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:10, pp:1017-1027 [Journal]
  35. TingTing Hwang, Robert Michael Owens, Mary Jane Irwin
    Efficiently computing communication complexity for multilevel logic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:5, pp:545-554 [Journal]
  36. TingTing Hwang, Robert Michael Owens, Mary Jane Irwin, Kuo-Hua Wang
    Logic synthesis for field-programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:10, pp:1280-1287 [Journal]
  37. Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin
    Performance-driven interconnection optimization for microarchitecture synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:137-149 [Journal]
  38. How-Rern Lin, TingTing Hwang
    On determining sensitization criterion in an iterative gate sizing process. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:231-238 [Journal]
  39. Shiuann-Shiuh Lin, Yuh-Ju Lin, TingTing Hwang
    Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:316-320 [Journal]
  40. Kuo-Hua Wang, TingTing Hwang
    Boolean matching for incompletely specified functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:2, pp:160-168 [Journal]
  41. Kuo-Hua Wang, TingTing Hwang, Cheng Chen
    Exploiting communication complexity for Boolean matching. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1249-1256 [Journal]
  42. Sue-Hong Chow, Yi-Cheng Ho, TingTing Hwang, C. L. Liu
    Low power realization of finite state machines - a decomposition approach. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1996, v:1, n:3, pp:315-340 [Journal]
  43. Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu
    Logic transformation for low-power synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:2, pp:265-283 [Journal]
  44. Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai
    Compiler optimization on VLIW instruction scheduling for low power. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:2, pp:252-268 [Journal]
  45. Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
    Decomposition of instruction decoders for low-power designs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:4, pp:880-889 [Journal]
  46. Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang
    Crosstalk minimization in logic synthesis for PLAs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:4, pp:890-915 [Journal]
  47. Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu
    A power-driven multiplication instruction-set design method for ASIPs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:81-85 [Journal]
  48. Chi Ta Wu, Ang-Chih Hsieh, TingTing Hwang
    Instruction buffering for nested loops in low-power design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:780-784 [Journal]
  49. Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu
    Performance-driven crosstalk elimination at post-compiler level. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  50. Ang-Chih Hsieh, Tzu-Teng Lin, Tsuang-Wei Chang, TingTing Hwang
    A functionality-directed clustering technique for low-power MTCMOS design - computation of simultaneously discharging current. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal]
  51. Chau-Shen Chen, TingTing Hwang, C. L. Liu
    Architecture driven circuit partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:383-389 [Journal]

  52. Thermal-aware post compilation for VLIW architectures. [Citation Graph (, )][DBLP]


  53. New spare cell design for IR drop minimization in Engineering Change Order. [Citation Graph (, )][DBLP]


  54. Thermal-aware memory mapping in 3D designs. [Citation Graph (, )][DBLP]


  55. A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test. [Citation Graph (, )][DBLP]


  56. TSV redundancy: Architecture and design issues in 3D IC. [Citation Graph (, )][DBLP]


  57. Skew aware polarity assignment in clock tree. [Citation Graph (, )][DBLP]


  58. Transition-aware decoupling-capacitor allocation in power noise reduction. [Citation Graph (, )][DBLP]


  59. A power-driven multiplication instruction-set design method for ASIPs. [Citation Graph (, )][DBLP]


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