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Ting-Chi Wang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jan-Yang Chang, Yu-Chen Liu, Ting-Chi Wang
    Faster and Better Spectral Algorithms for Multi-Way Partitioning. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:81-0 [Conf]
  2. Jianbang Lai, Ming-Shiun Lin, Ting-Chi Wang, Li-C. Wang
    Module placement with boundary constraints using the sequence-pair representation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:515-520 [Conf]
  3. Hsun-Cheng Lee, Ting-Chi Wang
    Feasible two-way circuit partitioning with complex resource constraints. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:435-440 [Conf]
  4. Kuang-Yao Lee, Ting-Chi Wang
    Post-routing redundant via insertion for yield/reliability improvement. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:303-308 [Conf]
  5. Zhong-Ching Lu, Ting-Chi Wang
    Concurrent flip-flop and buffer insertion with adaptive blockage avoidance. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:19-22 [Conf]
  6. Zhi-Hong Wang, En-Cheng Liu, Jianbang Lai, Ting-Chi Wang
    Power minization in LUT-based FPGA technology mapping. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:635-640 [Conf]
  7. Yun-Ru Wu, Ming-Chao Tsai, Ting-Chi Wang
    Maze routing with OPC consideration. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:198-203 [Conf]
  8. Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer
    On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:151-0 [Conf]
  9. Ting-Chi Wang, D. F. Wong
    An Optimal Algorithm for Floorplan Area Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:180-186 [Conf]
  10. Ting-Chi Wang, D. F. Wong
    A Graph Theoretic Technique to Speed up Floorplan Area Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:62-68 [Conf]
  11. Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu
    Routing for symmetric FPGAs and FPICs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:486-490 [Conf]
  12. Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao
    Post-routing redundant via insertion and line end extension with via density consideration. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:633-640 [Conf]
  13. Yao-Ping Chen, Ting-Chi Wang, D. F. Wong
    A Graph Partitioning Problem for Multiple-chip Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1778-1781 [Conf]
  14. Hao-Yueh Hsieh, Ting-Chi Wang
    Simple yet effective algorithms for block and I/O buffer placement in flip-chip design. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1879-1882 [Conf]
  15. Yi-He Jiang, Jianbang Lai, Ting-Chi Wang
    Module placement with pre-placed modules using the B*-tree representation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:347-350 [Conf]
  16. S. Dhamdhere, Ningyu Zhou, Ting-Chi Wang
    Module placement with pre-placed modules using the corner block list representation. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:349-352 [Conf]
  17. Cliff C. N. Sze, Ting-Chi Wang
    Optimal circuit clustering with variable interconnect delay. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:707-710 [Conf]
  18. En-Cheng Liu, Ming-Shiun Lin, Jianbang Lai, Ting-Chi Wang
    Slicing floorplan design with boundary-constrained modules. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:124-129 [Conf]
  19. Cliff C. N. Sze, Ting-Chi Wang
    Multi-Level Circuit Clustering for Delay Minimization. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:227-232 [Conf]
  20. T. W. Her, Ting-Chi Wang, Martin D. F. Wong
    Performance-driven channel pin assignment algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:7, pp:849-857 [Journal]
  21. Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu
    Routing for symmetric FPGAs and FPICs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:20-31 [Journal]
  22. Cliff C. N. Sze, Ting-Chi Wang
    Optimal circuit clustering for delay minimization under a more general delay model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:646-651 [Journal]
  23. Cliff C. N. Sze, Ting-Chi Wang, Li-C. Wang
    Multilevel circuit clustering for delay minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1073-1085 [Journal]
  24. Ting-Chi Wang, Martin D. F. Wong
    Optimal floorplan area optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:8, pp:992-1002 [Journal]
  25. Ting-Chi Wang, Martin D. F. Wong, Yachyang Sun, Chak-Kuen Wong
    Optimal net assignment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:2, pp:265-269 [Journal]

  26. Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability. [Citation Graph (, )][DBLP]


  27. A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction. [Citation Graph (, )][DBLP]


  28. Fast Buffered Delay Estimation Considering Process Variations. [Citation Graph (, )][DBLP]


  29. A new global router for modern designs. [Citation Graph (, )][DBLP]


  30. An MILP-based wire spreading algorithm for PSM-aware layout modification. [Citation Graph (, )][DBLP]


  31. A generalized network flow based algorithm for power-aware FPGA memory mapping. [Citation Graph (, )][DBLP]


  32. Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design. [Citation Graph (, )][DBLP]


  33. NTHU-Route 2.0: a fast and stable global router. [Citation Graph (, )][DBLP]


  34. Pad assignment for die-stacking System-in-Package design. [Citation Graph (, )][DBLP]


  35. Robust layer assignment for via optimization in multi-layer global routing. [Citation Graph (, )][DBLP]


  36. Redundant via insertion with wire bending. [Citation Graph (, )][DBLP]


  37. Optimal post-routing redundant via insertion. [Citation Graph (, )][DBLP]


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