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H. Narayanan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. M. V. Atre, P. S. Subramanian, H. Narayanan
    T4: Mathematical Methods in VLSI. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:18-19 [Conf]
  2. Sachin B. Patkar, H. Narayanan
    Fast On-Line/Off-Line Algorithms for Optimal Reinforcement of a Network and Its Connections with Principal Partition. [Citation Graph (0, 0)][DBLP]
    FSTTCS, 2000, pp:94-105 [Conf]
  3. Sachin B. Patkar, H. Narayanan
    A Fast Algorithm for the Principle Partition of a Graph. [Citation Graph (0, 0)][DBLP]
    FSTTCS, 1991, pp:288-306 [Conf]
  4. Sachin B. Patkar, H. Narayanan
    Fast Sequential and Randomised Parallel Algorithms for Rigidity and approximate Min k-cut. [Citation Graph (0, 0)][DBLP]
    FSTTCS, 1992, pp:265-278 [Conf]
  5. Rupesh S. Shelar, Madhav P. Desai, H. Narayanan
    Decomposition of Finite State Machines for Area, Delay Minimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:620-625 [Conf]
  6. Sachin B. Patkar, H. Narayanan
    Principal Lattice of Partition of submodular functions on Graphs: Fast algorithms for Principal Partition and Generic Rigidity. [Citation Graph (0, 0)][DBLP]
    ISAAC, 1992, pp:41-50 [Conf]
  7. Subir Roy, H. Narayanan
    Application of the principal partition and principal lattice of partitions of a graph to the problem of decomposition of a finite state machine. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2564-2567 [Conf]
  8. H. Narayanan, Subir Roy, Sachin B. Patkar
    Approximation Algorithms for Min-k-overlap Problems Using the Principal Lattice of Partitions Approach. [Citation Graph (0, 0)][DBLP]
    MFCS, 1994, pp:525-535 [Conf]
  9. H. Narayanan, Huzur Saran, Vijay V. Vazirani
    Randomized Parallel Algorithms for Matroid Union and Intersection, with Applications to Arboresences and Edge-Disjoint Spanning Trees. [Citation Graph (0, 0)][DBLP]
    SODA, 1992, pp:357-366 [Conf]
  10. Shabbir H. Batterywala, H. Narayanan
    Spectral Algorithm To Compute And Synthesize Reduced Order Passive Models For Arbitrary Rc Multiports. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:500-0 [Conf]
  11. Shabbir H. Batterywala, H. Narayanan
    Efficient DC Analysis of RVJ Circuits for Moment and Derivative Commutations of Interconnect Networks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:169-174 [Conf]
  12. M. V. Atre, P. S. Subramanian, H. Narayanan
    Mathematical Methods in VLSI (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:18-19 [Conf]
  13. B. N. V. Malleswara Gupta, H. Narayanan, Madhav P. Desai
    A State Assignment Scheme Targeting Performance and Area. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:378-383 [Conf]
  14. Sachin B. Patkar, Shabbir H. Batterywala, M. Chandramouli, H. Narayanan
    A New Partitioning Strategy Based on Supermodular Functions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:32-37 [Conf]
  15. Sachin B. Patkar, H. Narayanan
    An Efficient Practical Heuristic For Good Ratio-Cut Partitioning. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:64-69 [Conf]
  16. Gaurav Trivedi, Madhav P. Desai, H. Narayanan
    Fast DC Analysis and Its Application to Combinatorial Optimization Problems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:695-700 [Conf]
  17. Gaurav Trivedi, Sumit Punglia, H. Narayanan
    Application of DC Analyzer to Combinatorial Optimization Problems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:869-874 [Conf]
  18. Gaurav Trivedi, Madhav P. Desai, H. Narayanan
    Parallelization of DC Analysis through Multiport Decomposition. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:863-868 [Conf]
  19. Madhav P. Desai, H. Narayanan, Sachin B. Patkar
    The realization of finite state machines by decomposition and the principal lattice of partitions of a submodular function. [Citation Graph (0, 0)][DBLP]
    Discrete Applied Mathematics, 2003, v:131, n:2, pp:299-310 [Journal]
  20. H. Narayanan
    A note on the minimization of symmetric and general submodular functions. [Citation Graph (0, 0)][DBLP]
    Discrete Applied Mathematics, 2003, v:131, n:2, pp:513-522 [Journal]
  21. Sachin B. Patkar, H. Narayanan
    Improving graph partitions using submodular functions. [Citation Graph (0, 0)][DBLP]
    Discrete Applied Mathematics, 2003, v:131, n:2, pp:535-553 [Journal]
  22. Sachin B. Patkar, H. Narayanan
    A note on optimal covering augmentation for graphic polymatroids. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 2001, v:79, n:6, pp:285-290 [Journal]
  23. H. Narayanan, Subir Roy, Sachin B. Patkar
    Approximation Algorithms for Min-k-Overlap Problems Using the Principal Lattice of Partitions Approach. [Citation Graph (0, 0)][DBLP]
    J. Algorithms, 1996, v:21, n:2, pp:306-330 [Journal]
  24. Sachin B. Patkar, H. Narayanan
    Fast On-Line/Off-Line Algorithms for Optimal Reinforcement of a Network and its Connections with Principal Partition. [Citation Graph (0, 0)][DBLP]
    J. Comb. Optim., 2003, v:7, n:1, pp:45-68 [Journal]
  25. H. Narayanan, Huzur Saran, Vijay V. Vazirani
    Randomized Parallel Algorithms for Matroid Union and Intersection, With Applications to Arboresences and Edge-Disjoint Spanning Trees. [Citation Graph (0, 0)][DBLP]
    SIAM J. Comput., 1994, v:23, n:2, pp:387-397 [Journal]
  26. Gaurav Trivedi, H. Narayanan
    Application of Fast DC Analysis to Partitioning Hypergraphs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3407-3410 [Conf]

  27. Exploiting Hybrid Analysis in Solving Electrical Networks. [Citation Graph (, )][DBLP]


  28. FPGA Based High Performance Double-Precision Matrix Multiplication. [Citation Graph (, )][DBLP]


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