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Luis Miguel Silveira: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Edoardo Charbon, Luis Miguel Silveira, Paolo Miliozzi
    A benchmark suite for substrate analysis. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:617-622 [Conf]
  2. Carlos P. Coelho, Joel R. Phillips, Luis Miguel Silveira
    Robust Rational Function Approximation Algorithm for Model Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:207-212 [Conf]
  3. Mattan Kamon, Nuno Alexandre Marques, Yehia Massoud, Luis Miguel Silveira, Jacob White
    Interconnect Analysis: From 3-D Structures to Circuit Models. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:910-914 [Conf]
  4. Nuno Alexandre Marques, Mattan Kamon, Jacob White, Luis Miguel Silveira
    A Mixed Nodal-Mesh Formulation for Efficient Extraction and Passive Reduced-Order Modeling of 3D Interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:297-302 [Conf]
  5. Joel R. Phillips, Luca Daniel, Luis Miguel Silveira
    Guaranteed passive balancing transformations for model order reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:52-57 [Conf]
  6. Luis Miguel Silveira, Ibrahim M. Elfadel, Jacob White, Moni Chilukuri, Kenneth S. Kundert
    An Efficient Approach to Transmission Line Simulation Using Measured or Tabulated S-parameter Data. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:634-639 [Conf]
  7. Luis Miguel Silveira, Mattan Kamon, Jacob White
    Efficient Reduced-Order Modeling of Frequency-Dependent Coupling Inductances Associated with 3-D Interconnect Structures. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:376-380 [Conf]
  8. Luis Miguel Silveira, Joel R. Phillips
    Exploiting input information in a model reduction algorithm for massively coupled parasitic networks. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:385-388 [Conf]
  9. Carlos P. Coelho, Luis Miguel Silveira, Joel R. Phillips
    Passive Constrained Rational Approximation Algorithm Using Nevanlinna-Pick Interpolation. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:923-930 [Conf]
  10. Nuno Alexandre Marques, Mattan Kamon, Jacob White, Luis Miguel Silveira
    An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:538-543 [Conf]
  11. Joel R. Phillips, Luis Miguel Silveira
    Poor Man's TBR: A Simple Model Reduction Scheme. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:938-943 [Conf]
  12. Luís Guerra e Silva, Luis Miguel Silveira, João P. Marques Silva
    Algorithms for Solving Boolean Satisfiability in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:526-530 [Conf]
  13. Luís Guerra e Silva, Luis Miguel Silveira
    Grid-based statistical timing analysis. [Citation Graph (0, 0)][DBLP]
    IADIS AC, 2005, pp:73-80 [Conf]
  14. Carlos P. Coelho, Joel R. Phillips, Luis Miguel Silveira
    A Convex Programming Approach to Positive Real Rational Approximation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:245-251 [Conf]
  15. Carlos P. Coelho, Joel R. Phillips, Luis Miguel Silveira
    Optimization based passive constrained fitting. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:775-780 [Conf]
  16. Joel R. Phillips, João Afonso, Arlindo L. Oliveira, Luis Miguel Silveira
    Analog Macromodeling using Kernel Methods. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:446-453 [Conf]
  17. Joel R. Phillips, Luis Miguel Silveira
    Simulation Approaches for Strongly Coupled Interconnect Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:430-0 [Conf]
  18. Luis Miguel Silveira, Mattan Kamon, Ibrahim M. Elfadel, Jacob White
    A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:288-294 [Conf]
  19. Luis Miguel Silveira, Andrew Lumsdaine, Jacob White
    Parallel Simulation Algorithms for Grid-Based Analog Signal Processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:442-445 [Conf]
  20. Luis Miguel Silveira, Jacob White, Steven Leeb
    A Modified Envelope-Following Approach to Clocked Analog Circuit Simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:20-23 [Conf]
  21. João M. S. Silva, Luís M. Silveira
    Multigrid-based substrate coupling model extraction. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:169-173 [Conf]
  22. João M. S. Silva, Luis Miguel Silveira
    Dynamic Models for Substrate Coupling in Mixed-Mode Systems. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:25-30 [Conf]
  23. Luis Miguel Silveira, Nuno Vargas
    Characterizing Substrate Coupling in Deep-Submicron Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:2, pp:4-15 [Journal]
  24. Carlos P. Coelho, Joel R. Phillips, Luis Miguel Silveira
    A convex programming approach for generating guaranteed passive approximations to tabulated frequency-data. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:293-301 [Journal]
  25. Joao Paulo Costa, Mike Chou, Luis Miguel Silveira
    Efficient techniques for accurate modeling and simulation ofsubstrate coupling in mixed-signal IC's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:597-607 [Journal]
  26. Andrew Lumsdaine, Luis Miguel Silveira, Jacob K. White
    Massively parallel simulation algorithms for grid-based analog signal processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1665-1678 [Journal]
  27. Joel R. Phillips, Luca Daniel, Luis Miguel Silveira
    Guaranteed passive balancing transformations for model order reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1027-1041 [Journal]
  28. Joel R. Phillips, Luis Miguel Silveira
    Poor man's TBR: a simple model reduction scheme. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:43-55 [Journal]
  29. Luis Miguel Silveira, Jacob K. White, Horácio C. Neto, Luís M. Vidigal
    On exponential fitting for circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:5, pp:566-574 [Journal]
  30. Luís Guerra e Silva, João P. Marques Silva, Luis Miguel Silveira, Karem A. Sakallah
    Satisfiability models and algorithms for circuit delay computation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:1, pp:137-158 [Journal]
  31. Luís Guerra e Silva, Luis Miguel Silveira, Joel R. Phillips
    Efficient computation of the worst-delay corner. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1617-1622 [Conf]

  32. ARMS - automatic residue-minimization based sampling for multi-point modeling techniques. [Citation Graph (, )][DBLP]


  33. Efficient Representation and Analysis of Power Grids. [Citation Graph (, )][DBLP]


  34. SPARE - a Scalable algorithm for passive, structure preserving, Parameter-Aware model order REduction. [Citation Graph (, )][DBLP]


  35. On the efficient reduction of complete EM based parametric models. [Citation Graph (, )][DBLP]


  36. HORUS - high-dimensional Model Order Reduction via low moment-matching upgraded sampling. [Citation Graph (, )][DBLP]


  37. Fast and reliable passivity assessment and enforcement with extended Hamiltonian pencil. [Citation Graph (, )][DBLP]


  38. Generating Worst-Case Stimuli for Accurate Power Grid Analysis. [Citation Graph (, )][DBLP]


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