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Valeria Bertacco: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Todd M. Austin, Valeria Bertacco, David Blaauw, Trevor N. Mudge
    Opportunities and challenges for better than worst-case design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:2-7 [Conf]
  2. Stephen Plaza, Valeria Bertacco
    STACCATO: disjoint support decompositions from BDDs through symbolic kernels. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:276-279 [Conf]
  3. Ilya Wagner, Valeria Bertacco, Todd M. Austin
    Depth-driven verification of simultaneous interfaces. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:442-447 [Conf]
  4. Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, Todd M. Austin
    Ultra low-cost defect protection for microprocessor pipelines. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2006, pp:73-82 [Conf]
  5. Valeria Bertacco, Maurizio Damiani, Stefano Quer
    Cycle-Based Symbolic Simulation of Gate-Level Synchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:391-396 [Conf]
  6. Valeria Bertacco, Kunle Olukotun
    Efficient state representation for symbolic simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:99-104 [Conf]
  7. Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David Blaauw, Trevor N. Mudge
    Circuit-aware architectural simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:305-310 [Conf]
  8. Ilya Wagner, Valeria Bertacco, Todd M. Austin
    StressTest: an automatic approach to test generation via activity monitors. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:783-788 [Conf]
  9. Ilya Wagner, Valeria Bertacco, Todd M. Austin
    Shielding against design flaws with field repairable control logic. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:344-347 [Conf]
  10. Smitha Shyam, Valeria Bertacco
    Distance-guided hybrid verification with GUIDO. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1211-1216 [Conf]
  11. Valeria Bertacco, Maurizio Damiani
    Boolean Function Representation Using Parallel-Access Diagrams. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:112-117 [Conf]
  12. Valeria Bertacco, Maurizio Damiani
    The disjunctive decomposition of logic functions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:78-82 [Conf]
  13. Kai-Hui Chang, Valeria Bertacco, Igor L. Markov
    Simulation-based bug trace minimization with BMC-based refinement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:1045-1051 [Conf]
  14. Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
    Post-placement rewiring and rebuffering by exhaustive search for functional symmetries. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:56-63 [Conf]
  15. Pei-Hsin Ho, Thomas R. Shiple, Kevin Harer, James H. Kukula, Robert F. Damiano, Valeria Bertacco, Jerry Taylor, Jiang Long
    Smart Simulation Using Collaborative Formal and Simulation Engines. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:120-126 [Conf]
  16. Beth Isaksen, Valeria Bertacco
    Verification through the principle of least astonishment. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:860-867 [Conf]
  17. Valeria Bertacco, Maurizio Damiani
    Boolean Function Representation Based on Disjoint-Support Decompositions. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:27-0 [Conf]
  18. Todd M. Austin, Valeria Bertacco
    Deployment of Better Than Worst-Case Design: Solutions and Needs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:550-558 [Conf]
  19. Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M. Austin, Trevor N. Mudge
    Microarchitectural power modeling techniques for deep sub-micron microprocessors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:212-217 [Conf]
  20. Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco
    InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:487-494 [Conf]
  21. Valeria Bertacco
    Formal verification for real-world designs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:5- [Conf]
  22. Valeria Bertacco
    Low maintenance verification. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:12- [Conf]
  23. Ilya Wagner, Valeria Bertacco
    Engineering trust with semantic guardians. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:743-748 [Conf]
  24. Mojtaba Mehrara, Mona Attariyan, Smitha Shyam, Kypros Constantinides, Valeria Bertacco, Todd M. Austin
    Low-cost protection for SER upsets and silicon defects. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1146-1151 [Conf]
  25. Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang, Michael Orshansky
    Architecting a reliable CMP switch architecture. [Citation Graph (0, 0)][DBLP]
    TACO, 2007, v:4, n:1, pp:- [Journal]
  26. Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
    Postplacement rewiring by exhaustive search for functional symmetries. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal]

  27. Node Mergers in the Presence of Don't Cares. [Citation Graph (, )][DBLP]


  28. Safe Delay Optimization for Physical Synthesis. [Citation Graph (, )][DBLP]


  29. Fixing Design Errors with Counterexamples and Resynthesis. [Citation Graph (, )][DBLP]


  30. Human computing for EDA. [Citation Graph (, )][DBLP]


  31. Vicis: a reliable network for unreliable silicon. [Citation Graph (, )][DBLP]


  32. Event-driven gate-level simulation with GP-GPUs. [Citation Graph (, )][DBLP]


  33. Debugging strategies for mere mortals. [Citation Graph (, )][DBLP]


  34. Bridging pre-silicon verification and post-silicon validation. [Citation Graph (, )][DBLP]


  35. Electronic design automation for social networks. [Citation Graph (, )][DBLP]


  36. MCjammer: Adaptive Verification for Multi-core Designs. [Citation Graph (, )][DBLP]


  37. Random Stimulus Generation using Entropy and XOR Constraints. [Citation Graph (, )][DBLP]


  38. Caspar: Hardware patching for multicore processors. [Citation Graph (, )][DBLP]


  39. Customizing IP cores for system-on-chip designs using extensive external don't-cares. [Citation Graph (, )][DBLP]


  40. A highly resilient routing algorithm for fault-tolerant NoCs. [Citation Graph (, )][DBLP]


  41. GCS: High-performance gate-level simulation with GPGPUs. [Citation Graph (, )][DBLP]


  42. Fault-based attack of RSA authentication. [Citation Graph (, )][DBLP]


  43. BulletProof: a defect-tolerant CMP switch architecture. [Citation Graph (, )][DBLP]


  44. Dacota: Post-silicon validation of the memory subsystem in multi-core designs. [Citation Graph (, )][DBLP]


  45. Automating post-silicon debugging and repair. [Citation Graph (, )][DBLP]


  46. Post-silicon verification for cache coherence. [Citation Graph (, )][DBLP]


  47. CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework. [Citation Graph (, )][DBLP]


  48. Reversi: Post-silicon validation system for modern microprocessors. [Citation Graph (, )][DBLP]


  49. Reap what you sow: spare cells for post-silicon metal fix. [Citation Graph (, )][DBLP]


  50. Optimizing non-monotonic interconnect using functional simulation and logic restructuring. [Citation Graph (, )][DBLP]


  51. Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation. [Citation Graph (, )][DBLP]


  52. Testudo: Heavyweight security analysis via statistical sampling. [Citation Graph (, )][DBLP]


  53. Chico: An On-chip Hardware Checker for Pipeline Control Logic. [Citation Graph (, )][DBLP]


  54. Automating Postsilicon Debugging and Repair. [Citation Graph (, )][DBLP]


  55. Reliable Systems on Unreliable Fabrics. [Citation Graph (, )][DBLP]


  56. Incremental Verification with Error Detection, Diagnosis, and Visualization. [Citation Graph (, )][DBLP]


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